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technical data DSP56303/d rev. 10, 6/2004 24-bit digital signal processor figure 1. DSP56303 block diagram pll once? clock generator internal data bus switch yab xab pab ydb xdb pdb gdb modb/irqb modc/irqc external data bus switch 13 modd/irqd dsp56300 6 16 24-bit 24 18 ddb dab peripheral core ym_eb xm_eb pm_eb pio_eb expansion area 6 jtag 5 3 reset moda/irqa pinit/nmi 2 bootstrap rom extal xtal address control data address generation unit six-channel dma unit program interrupt controller program decode controller program address generator data alu 24 24 + 56 56-bit mac two 56-bit accumulators 56-bit barrel shifter power management external bus interface and inst. cache control external address bus switch memory expansion area de x data ram 2048 24 bits (default) y data ram 2048 24 bits (default) triple timer hi08 essi sci program 4096 24 bits (default) ram the DSP56303 is intended for use in telecommunication applications, such as multi-line voice/data/ fax processing, video conferencing, audio applications, control, and general digital signal processing. the DSP56303 is a member of the dsp56300 core family of programmable cmos digital signal processors (dsps). this family uses a high-performance, single clock cycle per instruction engine providing a twofold performance increase over motorola?s popular dsp56000 core family while retaining code compatibility. significant architectural features of the dsp56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and dma. the DSP56303 offers 100 mips using an internal 100 mhz clock at 3.0?3.6 volts. the dsp56300 core family offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power to enable wireless, telecommunications, and multimedia products. what?s new? rev. 10 updates the example clock input circuits in figure 2-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ii table of contents DSP56303 features.............................................................................................................. .............................. iii target applications ............................................................................................................ ................................ iv product documentation.......................................................................................................... ............................ iv chapter 1 signal/ connection descriptions 1.1 signal groupings............................................................................................................ .................................. 1-1 1.2 power....................................................................................................................... ......................................... 1-3 1.3 ground...................................................................................................................... ........................................ 1-3 1.4 clock ....................................................................................................................... ......................................... 1-4 1.5 pll......................................................................................................................... .......................................... 1-4 1.6 external memory expansion port (port a)..................................................................................... ................. 1-5 1.7 interrupt and mode control .................................................................................................. ........................... 1-8 1.8 host interface (hi08) ....................................................................................................... ................................ 1-9 1.9 enhanced synchronous serial interface 0 (essi0)............................................................................. ........... 1-13 1.10 enhanced synchronous serial interface 1 (essi1)............................................................................ ............ 1-14 1.11 serial communication interface (sci)....................................................................................... .................... 1-16 1.12 timers..................................................................................................................... ........................................ 1-17 1.13 jtag and once interface .................................................................................................... ......................... 1-18 chapter 2 specifications 2.1 introduction ................................................................................................................ ...................................... 2-1 2.2 maximum ratings ............................................................................................................. ............................... 2-1 2.4 thermal characteristics ..................................................................................................... .............................. 2-2 2.5 dc electrical characteristics ............................................................................................... ............................ 2-3 2.6 ac electrical characteristics ............................................................................................... ............................ 2-4 chapter 3 packaging 3.1 pin-out and package information ............................................................................................. ....................... 3-1 3.2 tqfp package description .................................................................................................... .......................... 3-2 3.3 tqfp package mechanical drawing ............................................................................................. .................. 3-9 3.4 map-bga package description ................................................................................................. .................. 3-10 3.5 map-bga package mechanical drawing .......................................................................................... .......... 3-19 chapter 4 design considerations 4.1 thermal design considerations ............................................................................................... ........................ 4-1 4.2 electrical design considerations ............................................................................................ ......................... 4-2 4.3 power consumption considerations ............................................................................................ .................... 4-4 4.4 pll performance issues ...................................................................................................... ............................ 4-5 4.5 input (extal) jitter requirements........................................................................................... ...................... 4-5 appendix a power consumption benchmark index data sheet conventions overbar used to indicate a signal that is active when pulled low (for example, the reset pin is active when low.) ?asserted? means that a high true (active high) signal is high or that a low true (active low) signal is low ?deasserted? means that a high true (active high) signal is low or that a low true (active low) signal is high examples: signal/symbol logic state signal state voltage pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol note: values for v il , v ol , v ih , and v oh are defined by individual product specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
iii DSP56303 features high-performance dsp56300 core 100 million instructions per second (mips) with a 100 mhz clock at 3.3 v nominal object code compatible with the dsp56000 core with highly parallel instruction set data arithmetic logic unit (data alu) with fully pipelined 24 24-bit parallel multiplier-accumulator (mac), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional alu instructions, and 24-bit or 16-bit arithmetic support under software control program control unit (pcu) with position independent code (pic) support, addressing modes optimized for dsp applications (including immediate offsets), internal instruction cache controller, internal memory-expandable hardware stack, nested hardware do loops, and fast auto-return interrupts direct memory access (dma) with six dma channels supporting internal and external accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and triggering from interrupt lines and all peripherals phase lock loop (pll) allows change of low-power divide factor (df) without loss of lock and output clock with skew elimination hardware debugging support including on-chip emulation (once ? ) module, joint test action group (jtag) test access port (tap) internal peripherals enhanced dsp56000-like 8-bit parallel host interface (hi08) supports a variety of buses (for example, isa) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and dsps two enhanced synchronous serial interfaces (essi), each with one receiver and three transmitters (allows six-channel home theater) serial communications interface (sci) with baud rate generator triple timer module up to thirty-four programmable general-purpose input/output (gpio) pins, depending on which peripherals are enabled internal memories 192 24-bit bootstrap rom 8 k 24-bit ram total program ram, instruction cache, x data ram, and y data ram sizes are programmable: program ram size instruction cache size x data ram size y data ram size instruction cache switch mode 4096 24-bit 0 2048 24-bit 2048 24-bit disabled disabled 3072 24-bit 1024 24-bit 2048 24-bit 2048 24-bit enabled disabled 2048 24-bit 0 3072 24-bit 3072 24-bit disabled enabled 1024 24-bit 1024 24-bit 3072 24-bit 3072 24-bit enabled enabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
iv external memory expansion data memory expansion to two 256 k 24-bit word memory spaces using the standard external address lines program memory expansion to one 256 k 24-bit words memory space using the standard external address lines external memory expansion port chip select logic for glueless interface to static random access memory (srams) internal dram controller for glueless interface to dynamic random access memory (drams) reduced power dissipation very low-power cmos design wait and stop low-power standby modes fully static design specified to operate down to 0 hz (dc) optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent) packaging the DSP56303 is available in a 144-pin tqfp package or a 196-pin map-bga package. target applications multi-line voice/data/fax processing video conferencing audio applications control product documentation the three documents listed in the following table are required for a complete description of the DSP56303 and are necessary to design properly with the part. documentation is available from the following sources. (see the back cover for details.) a local motorola distributor a motorola semiconductor sales office a motorola literature distribution center the world wide web (www) table 1. DSP56303 documentation name description order number dsp56300 family manual detailed description of the dsp56300 family processor core and instruction set dsp56300fm/ad DSP56303 user?s manual detailed functional description of the DSP56303 memory configuration, operation, and register programming DSP56303um/d DSP56303 technical data DSP56303 features list and physical, electrical, timing, and package specifications DSP56303/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-1 chapter 1 signal/ connection descriptions 1.1 signal groupings the DSP56303 input and output signals are organized into functional groups as shown in tab le 1-1 . figure 1-1 diagrams the DSP56303 signals by functional group. the remainder of this chapter describes the signal pins in each functional group. note: this chapter refers to a number of configuration registers used to select individual multiplexed signal functionality. refer to the DSP56303 user?s manual for details on these configuration registers. table 1-1. DSP56303 functional signal groupings functional group number of signals tqfp map- bga power (v cc ) 18 18 ground (gnd) 19 66 clock 22 pll 33 address bus port a 1 18 18 data bus 24 24 bus control 13 13 interrupt and mode control 5 5 host interface (hi08) port b 2 16 16 enhanced synchronous serial interface (essi) ports c and d 3 12 12 serial communication interface (sci) port e 4 33 timer 33 once/jtag port 66 notes: 1. port a signals define the external memory interface port, including the external address bus, data bus, and control signals. 2. port b signals are the hi08 port signals multiplexed with the gpio signals. 3. port c and d signals are the two essi port signals multiplexed with the gpio signals. 4. port e signals are the sci port signals multiplexed with the gpio signals. 5. there are 2 signal connections in the tqfp package and 7 signal connections in the map-bga package that are not used. these are designated as no connect (nc) in the package description (see chapter 3 ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-2 signal groupings figure 1-1. signals identified by functional group notes: 1. the hi08 port supports a non-multiplexed or a multiplexed bus, single or double data strobe (ds), and single or double host request (hr) configurations. since each of these modes is configured independently, any combination of these modes is possible. these hi08 signals can also be configured alternatively as gpio signals (pb[0?15]). signals with dual designations (for example, has /has) have configurable polarity. 2. the essi0, essi1, and sci signals are multiplexed with the port c gpio signals (pc[0?5]), port d gpio signals (pd[0?5]), and port e gpio signals (pe[0?2]), respectively. 3. tio[0?2] can be configured as gpio signals. 4. ground connections shown in this figure are for the tqfp package. in the map-bga package, in addition to the gnd p and gnd p1 connections, there are 64 gnd connections to a common internal package ground plane. DSP56303 24 18 external address bus external data bus external bus control enhanced synchronous serial interface port 0 (essi0) 2 timers 3 pll once/ jtag port power inputs: pll internal logic address bus data bus bus control hi08 essi/sci/timer a[0?17] d[0?23] aa0/ras0 ? aa3/ras3 rd wr ta br bg bb cas bclk bclk tck tdi tdo tms trst de clkout pcap after reset nmi v ccp v ccq v cca v ccd v ccc v cch v ccs 4 serial communications interface (sci) port 2 4 2 2 grounds 4 : pll pll internal logic address bus data bus bus control hi08 essi/sci/timer gnd p gnd p1 gnd q gnd a gnd d gnd c gnd h gnd s 4 interrupt/ mode control moda modb modc modd reset host interface (hi08) port 1 non-multiplexed bus h[0?7] ha0 ha1 ha2 hcs/ hcs single ds hrw hds /hds single hr hreq /hreq hack /hack rxd txd sclk sc0[0?2] sck0 srd0 std0 tio0 tio1 tio2 8 3 4 extal xtal clock enhanced synchronous serial interface port 1 (essi1) 2 sc1[0?2] sck1 srd1 std1 3 multiplexed bus had[0?7] has /has ha8 ha9 ha10 double ds hrd /hrd hwr /hwr double hr htrq /htrq hrrq /hrrq port b gpio pb[0?7] pb8 pb9 pb10 pb13 pb11 pb12 pb14 pb15 port e gpio pe0 pe1 pe2 port c gpio pc[0?2] pc3 pc4 pc5 port d gpio pd[0?2] pd3 pd4 pd5 timer gpio tio0 tio1 tio2 port a 4 irqa irqb irqc irqd pinit reset during reset after reset reset during 4 2 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-3 power 1.2 power 1.3 ground table 1-2. power inputs power name description v ccp pll power ?v cc dedicated for pll use. the voltage should be well-regulated and the input should be provided with an extremely low impedance path to the v cc power rail. v ccq quiet power ?an isolated power for the core processing logic. this input must be isolated externally from all other chip power inputs. v cca address bus power ?an isolated power for sections of the address bus i/o drivers. this input must be tied externally to all other chip power inputs, except v ccq . v ccd data bus power ?an isolated power for sections of the data bus i/o drivers. this input must be tied externally to all other chip power inputs, except v ccq . v ccc bus control power ?an isolated power for the bus control i/o drivers. this input must be tied externally to all other chip power inputs , except v ccq . v cch host power ?an isolated power for the hi08 i/o drivers. this input must be tied externally to all other chip power inputs , except v ccq . v ccs essi, sci, and timer power ?an isolated power for the essi, sci, and timer i/o drivers. this input must be tied externally to all other chip power inputs, except v ccq . note: the user must provide adequate external decoupling capacitors for all power connections. table 1-3. grounds 1 ground name description gnd p pll ground ?ground-dedicated for pll use. the connection should be provided with an extremely low-impedance path to ground. v ccp should be bypassed to gnd p by a 0.47 f capacitor located as close as possible to the chip package. gnd p1 pll ground 1 ?ground-dedicated for pll use. the connection should be provided with an extremely low-impedance path to ground. gnd q 2 quiet ground? an isolated ground for the internal processing logic. this connection must be tied externally to all other chip ground connections, except gnd p and gnd p1 . the user must provide adequate external decoupling capacitors. gnd a 2 address bus ground? an isolated ground for sections of the address bus i/o drivers. this connection must be tied externally to all other chip ground connections, except gnd p and gnd p1 . the user must provide adequate external decoupling capacitors. gnd d 2 data bus ground? an isolated ground for sections of the data bus i/o drivers. this connection must be tied externally to all other chip ground connections, except gnd p and gnd p1 . the user must provide adequate external decoupling capacitors. gnd c 2 bus control ground? an isolated ground for the bus control i/o drivers. this connection must be tied externally to all other chip ground connections, except gnd p and gnd p1 . the user must provide adequate external decoupling capacitors. gnd h 2 host ground? an isolated ground for the hi08 i/o drivers. this connection must be tied externally to all other chip ground connections, except gnd p and gnd p1 . the user must provide adequate external decoupling capacitors. gnd s 2 essi, sci, and timer ground? an isolated ground for the essi, sci, and timer i/o drivers. this connection must be tied externally to all other chip ground connections, except gnd p and gnd p1 . the user must provide adequate external decoupling capacitors. gnd 3 ground ?connected to an internal device ground plane. notes: 1. the user must provide adequate external decoupling capacitors for all gnd connections. 2. these connections are only used on the tqfp package. 3. these connections are common grounds used on the map-bga package. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-4 clock 1.4 clock 1.5 pll table 1-4. clock signals signal name type state during reset signal description extal input input external clock/crystal input ?interfaces the internal crystal oscillator input to an external crystal or an external clock. xtal output chip-driven crystal output ?connects the internal crystal oscillator output to an external crystal. if an external clock is used, leave xtal unconnected. table 1-5. phase-locked loop signals signal name type state during reset signal description clkout output chip-driven clock output? provides an output clock synchronized to the internal core clock phase. if the pll is enabled and both the multiplication and division factors equal one, then clkout is also synchronized to extal. if the pll is disabled, the clkout frequency is half the frequency of extal. pcap input input pll capacitor ?an input connecting an off-chip capacitor to the pll filter. connect one capacitor terminal to pcap and the other terminal to v ccp . if the pll is not used, pcap can be tied to v cc , gnd, or left floating. pinit nmi input input input pll initial ?during assertion of reset , the value of pinit is written into the pll enable (pen) bit of the pll control (pctl) register, determining whether the pll is enabled or disabled. nonmaskable interrupt ?after reset deassertion and during normal instruction processing, this schmitt-trigger input is the negative-edge-triggered nmi request internally synchronized to clkout. note : pinit/nmi can tolerate 5 v. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-5 external memory expansion port (port a) 1.6 external memory expansion port (port a) note: when the DSP56303 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant port a signals: a[0?17] , d[0?23] , aa0/ras0 ? aa3/ras3 , rd , wr , bb , cas . 1.6.1 external address bus 1.6.2 external data bus table 1-6. external address bus signals signal name type state during reset, stop, or wait signal description a[0?17] output tri-stated address bus ?when the dsp is the bus master, a[0?17] are active-high outputs that specify the address for external program and data memory accesses. otherwise, the signals are tri-stated. to minimize power dissipation, a[0?17] do not change state when external memory spaces are not being accessed. table 1-7. external data bus signals signal name type state during reset state during stop or wait signal description d[0?23] input/ output ignored input last state: input : ignored output : tri-stated data bus ?when the dsp is the bus master, d[0?23] are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. otherwise, d[0?23] are tri-stated. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-6 external memory expansion port (port a) 1.6.3 external bus control table 1-8. external bus control signals signal name type state during reset, stop, or wait signal description aa[0?3] ras[0?3] output output tri-stated address attribute ?when defined as aa, these signals can be used as chip selects or additional address lines. the default use defines a priority scheme under which only one aa signal can be asserted at a time. setting the aa priority disable (apd) bit (bit 14) of the operating mode register, the priority mechanism is disabled and the lines can be used together as four external lines that can be decoded externally into 16 chip select signals. row address strobe ?when defined as ras , these signals can be used as ras for dram interface. these signals are tri-statable outputs with programmable polarity. rd output tri-stated read enable ?when the dsp is the bus master, rd is an active-low output that is asserted to read external memory on the data bus (d[0?23]). otherwise, rd is tri-stated. wr output tri-stated write enable ?when the dsp is the bus master, wr is an active-low output that is asserted to write external memory on the data bus (d[0?23]). otherwise, the signals are tri-stated. ta input ignored input transfer acknowledge ?if the DSP56303 is the bus master and there is no external bus activity, or the DSP56303 is not the bus master, the ta input is ignored. the ta input is a data transfer acknowledge (dtack) function that can extend an external bus cycle indefinitely. any number of wait states (1, 2. . .infinity) can be added to the wait states inserted by the bus control register (bcr) by keeping ta deasserted. in typical operation, ta is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. the current bus cycle completes one clock period after ta is asserted synchronous to clkout. the number of wait states is determined by the ta input or by the bcr, whichever is longer. the bcr can be used to set the minimum number of wait states in external bus cycles. to use the ta functionality, the bcr must be programmed to at least one wait state. a zero wait state access cannot be extended by ta deassertion; otherwise, improper operation may result. ta can operate synchronously or asynchronously depending on the setting of the tas bit in the operating mode register. ta functionality cannot be used during dram type accesses; otherwise improper operation may result. br output reset: output (deasserted) state during stop/wait depends on brh bit setting: brh = 0: output, deasserted brh = 1: maintains last state (that is, if asserted, remains asserted) bus request ?asserted when the dsp requests bus mastership. br is deasserted when the dsp no longer needs the bus. br may be asserted or deasserted independently of whether the DSP56303 is a bus master or a bus slave. bus ?parking? allows br to be deasserted even though the DSP56303 is the bus master. (see the description of bus ?parking? in the bb signal description.) the bus request hold (brh) bit in the bcr allows br to be asserted under software control even though the dsp does not need the bus. br is typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. br is affected only by dsp requests for the external bus, never for the internal bus. during hardware reset, br is deasserted and the arbitration is reset to the bus slave state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-7 external memory expansion port (port a) bg input ignored input bus grant ?asserted by an external bus arbitration circuit when the DSP56303 becomes the next bus master. when bg is asserted, the DSP56303 must wait until bb is deasserted before taking bus mastership. when bg is deasserted, bus mastership is typically given up at the end of the current bus cycle. this may occur in the middle of an instruction that requires more than one external bus cycle for execution. the default operation of this bit requires a setup and hold time as specified in table 2-14 . an alternate mode can be invoked: set the asynchronous bus arbitration enable (abe) bit (bit 13) in the operating mode register. when this bit is set, bg and bb are synchronized internally. this eliminates the respective setup and hold time requirements but adds a required delay between the deassertion of an initial bg input and the assertion of a subsequent bg input. bb input/ output ignored input bus busy ?indicates that the bus is active. only after bb is deasserted can the pending bus master become the bus master (and then assert the signal again). the bus master may keep bb asserted after ceasing bus activity regardless of whether br is asserted or deasserted. called ?bus parking,? this allows the current bus master to reuse the bus without rearbitration until another device requires the bus. bb is deasserted by an ?active pull-up? method (that is, bb is driven high and then released and held high by an external pull-up resistor). the default operation of this signal requires a setup and hold time as specified in table 2-14 . an alternative mode can be invoked by setting the abe bit (bit 13) in the operating mode register. when this bit is set, bg and bb are synchronized internally. see bg for additional information. note : bb requires an external pull-up resistor. cas output tri-stated column address strobe ?when the dsp is the bus master, cas is an active-low output used by dram to strobe the column address. otherwise, if the bus mastership enable (bme) bit in the dram control register is cleared, the signal is tri-stated. bclk output tri-stated bus clock when the dsp is the bus master, bclk is active when the operating mode register address trace enable bit is set. when bclk is active and synchronized to clkout by the internal pll, bclk precedes clkout by one-fourth of a clock cycle. bclk output tri-stated bus clock not when the dsp is the bus master, bclk is the inverse of the bclk signal. otherwise, the signal is tri-stated. table 1-8. external bus control signals (continued) signal name type state during reset, stop, or wait signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-8 interrupt and mode control 1.7 interrupt and mode control the interrupt and mode control signals select the chip operating mode as it comes out of hardware reset. after reset is deasserted, these inputs are hardware interrupt request lines. table 1-9. interrupt and mode control signal name type state during reset signal description reset input schmitt-trigger input reset ?places the chip in the reset state and resets the internal phase generator. the schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. when the reset signal is deasserted, the initial chip operating mode is latched from the moda, modb, modc, and modd inputs. the reset signal must be asserted after powerup. moda irqa input input schmitt-trigger input mode select a ?moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into the operating mode register when the reset signal is deasserted. external interrupt request a ?after reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. if the processor is in the stop or wait standby state and irqa is asserted, the processor exits the stop or wait state. modb irqb input input schmitt-trigger input mode select b ?moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into the operating mode register when the reset signal is deasserted. external interrupt request b ?after reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. if the processor is in the wait standby state and irqb is asserted, the processor exits the wait state. modc irqc input input schmitt-trigger input mode select c ?moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into the operating mode register when the reset signal is deasserted. external interrupt request c ?after reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. if the processor is in the wait standby state and irqc is asserted, the processor exits the wait state. modd irqd input input schmitt-trigger input mode select d ?moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into the operating mode register when the reset signal is deasserted. external interrupt request d ?after reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. if the processor is in the wait standby state and irqd is asserted, the processor exits the wait state. note : these signals are all 5 v tolerant. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-9 host interface (hi08) 1.8 host interface (hi08) the hi08 provides a fast, 8-bit, parallel data port that connects directly to the host bus. the hi08 supports a variety of standard buses and connects directly to a number of industry-standard microcomputers, microprocessors, dsps, and dma hardware. 1.8.4 host port usage considerations careful synchronization is required when the system reads multiple-bit registers that are written by another asynchronous system. this is a common problem when two asynchronous systems are connected (as they are in the host port). the considerations for proper operation are discussed in table 1-10 . 1.8.5 host port configuration hi08 signal functions vary according to the programmed configuration of the interface as determined by the 16 bits in the hi08 port control register. table 1-10. host port usage considerations action description asynchronous read of receive byte registers when reading the receive byte registers, receive register high (rxh), receive register middle (rxm), or receive register low (rxl), the host interface programmer should use interrupts or poll the receive register data full (rxdf) flag that indicates data is available. this assures that the data in the receive byte registers is valid. asynchronous write to transmit byte registers the host interface programmer should not write to the transmit byte registers, transmit register high (txh), transmit register middle (txm), or transmit register low (txl), unless the transmit register data empty (txde) bit is set indicating that the transmit byte registers are empty. this guarantees that the transmit byte registers transfer valid data to the host receive (hrx) register. asynchronous write to host vector the host interface programmer must change the host vector (hv) register only when the host command bit (hc) is clear. this practice guarantees that the dsp interrupt control logic receives a stable vector. table 1-11. host interface signal name type state during reset 1,2 signal description h[0?7] had[0?7] pb[0?7] input/output input/output input or output ignored input host data? when the hi08 is programmed to interface with a non-multiplexed host bus and the hi function is selected, these signals are lines 0?7 of the bidirectional data bus. host address? when the hi08 is programmed to interface with a multiplexed host bus and the hi function is selected, these signals are lines 0?7 of the bidirectional multiplexed address/data bus. port b 0?7? when the hi08 is configured as gpio through the hi08 port control register, these signals are individually programmed as inputs or outputs through the hi08 data direction register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-10 host interface (hi08) ha0 has /has pb8 input input input or output ignored input host address input 0 ?when the hi08 is programmed to interface with a nonmultiplexed host bus and the hi function is selected, this signal is line 0 of the host address input bus. host address strobe? when the hi08 is programmed to interface with a multiplexed host bus and the hi function is selected, this signal is the host address strobe (has) schmitt-trigger input. the polarity of the address strobe is programmable but is configured active-low (has ) following reset. port b 8 ?when the hi08 is configured as gpio through the hi08 port control register, this signal is individually programmed as an input or output through the hi08 data direction register. ha1 ha8 pb9 input input input or output ignored input host address input 1 ?when the hi08 is programmed to interface with a nonmultiplexed host bus and the hi function is selected, this signal is line 1 of the host address (ha1) input bus. host address 8 ?when the hi08 is programmed to interface with a multiplexed host bus and the hi function is selected, this signal is line 8 of the host address (ha8) input bus. port b 9 ?when the hi08 is configured as gpio through the hi08 port control register, this signal is individually programmed as an input or output through the hi08 data direction register. ha2 ha9 pb10 input input input or output ignored input host address input 2 ?when the hi08 is programmed to interface with a nonmultiplexed host bus and the hi function is selected, this signal is line 2 of the host address (ha2) input bus. host address 9 ?when the hi08 is programmed to interface with a multiplexed host bus and the hi function is selected, this signal is line 9 of the host address (ha9) input bus. port b 10 ?when the hi08 is configured as gpio through the hi08 port control register, this signal is individually programmed as an input or output through the hi08 data direction register. hcs /hcs ha10 pb13 input input input or output ignored input host chip select ?when the hi08 is programmed to interface with a nonmultiplexed host bus and the hi function is selected, this signal is the host chip select (hcs) input. the polarity of the chip select is programmable but is configured active-low (hcs ) after reset. host address 10 ?when the hi08 is programmed to interface with a multiplexed host bus and the hi function is selected, this signal is line 10 of the host address (ha10) input bus. port b 13 ?when the hi08 is configured as gpio through the hi08 port control register, this signal is individually programmed as an input or output through the hi08 data direction register. table 1-11. host interface (continued) signal name type state during reset 1,2 signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-11 host interface (hi08) hrw hrd /hrd pb11 input input input or output ignored input host read/write ?when the hi08 is programmed to interface with a single-data-strobe host bus and the hi function is selected, this signal is the host read/write (hrw) input. host read data ?when the hi08 is programmed to interface with a double-data-strobe host bus and the hi function is selected, this signal is the hrd strobe schmitt-trigger input. the polarity of the data strobe is programmable but is configured as active-low (hrd ) after reset. port b 11 ?when the hi08 is configured as gpio through the hi08 port control register, this signal is individually programmed as an input or output through the hi08 data direction register. hds /hds hwr /hwr pb12 input input input or output ignored input host data strobe ?when the hi08 is programmed to interface with a single-data-strobe host bus and the hi function is selected, this signal is the host data strobe (hds) schmitt-trigger input. the polarity of the data strobe is programmable but is configured as active-low (hds ) following reset. host write data ?when the hi08 is programmed to interface with a double-data-strobe host bus and the hi function is selected, this signal is the host write data strobe (hwr) schmitt-trigger input. the polarity of the data strobe is programmable but is configured as active-low (hwr ) following reset. port b 12 ?when the hi08 is configured as gpio through the hi08 port control register, this signal is individually programmed as an input or output through the hi08 data direction register. hreq /hreq htrq /htrq pb14 output output input or output ignored input host request ?when the hi08 is programmed to interface with a single host request host bus and the hi function is selected, this signal is the host request (hreq) output. the polarity of the host request is programmable but is configured as active-low (hreq ) following reset. the host request may be programmed as a driven or open-drain output. transmit host request ?when the hi08 is programmed to interface with a double host request host bus and the hi function is selected, this signal is the transmit host request (htrq) output. the polarity of the host request is programmable but is configured as active-low (htrq ) following reset. the host request may be programmed as a driven or open-drain output. port b 14 ?when the hi08 is configured as gpio through the hi08 port control register, this signal is individually programmed as an input or output through the hi08 data direction register. table 1-11. host interface (continued) signal name type state during reset 1,2 signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-12 host interface (hi08) hack /hack hrrq /hrrq pb15 input output input or output ignored input host acknowledge ?when the hi08 is programmed to interface with a single host request host bus and the hi function is selected, this signal is the host acknowledge (hack) schmitt-trigger input. the polarity of the host acknowledge is programmable but is configured as active-low (hack ) after reset. receive host request ?when the hi08 is programmed to interface with a double host request host bus and the hi function is selected, this signal is the receive host request (hrrq) output. the polarity of the host request is programmable but is configured as active-low (hrrq ) after reset. the host request may be programmed as a driven or open-drain output. port b 15 ?when the hi08 is configured as gpio through the hi08 port control register, this signal is individually programmed as an input or output through the hi08 data direction register. notes: 1. in the stop state, the signal maintains the last state as follows: if the last state is input, the signal is an ignored input. if the last state is output, the signal is tri-stated. 2. the wait processing state does not affect the signal state. 3. all inputs are 5 v tolerant. table 1-11. host interface (continued) signal name type state during reset 1,2 signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-13 enhanced synchronous serial interface 0 (essi0) 1.9 enhanced synchronous serial interface 0 (essi0) two synchronous serial interfaces (essi0 and essi1) provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other dsps, microprocessors, and peripherals that implement the motorola serial peripheral interface (spi). table 1-12. enhanced synchronous serial interface 0 signal name type state during reset 1,2 signal description sc00 pc0 input or output input or output ignored input serial control 0 ?for asynchronous mode, this signal is used for the receive clock i/o (schmitt-trigger input). for synchronous mode, this signal is used either for transmitter 1 output or for serial i/o flag 0. port c 0 ?the default configuration following reset is gpio input pc0. when configured as pc0, signal direction is controlled through the port c direction register. the signal can be configured as essi signal sc00 through the port c control register. sc01 pc1 input/output input or output ignored input serial control 1 ?for asynchronous mode, this signal is the receiver frame sync i/o. for synchronous mode, this signal is used either for transmitter 2 output or for serial i/o flag 1. port c 1 ?the default configuration following reset is gpio input pc1. when configured as pc1, signal direction is controlled through the port c direction register. the signal can be configured as an essi signal sc01 through the port c control register. sc02 pc2 input/output input or output ignored input serial control signal 2 ?the frame sync for both the transmitter and receiver in synchronous mode, and for the transmitter only in asynchronous mode. when configured as an output, this signal is the internally generated frame sync signal. when configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). port c 2 ?the default configuration following reset is gpio input pc2. when configured as pc2, signal direction is controlled through the port c direction register. the signal can be configured as an essi signal sc02 through the port c control register. sck0 pc3 input/output input or output ignored input serial clock ?provides the serial bit rate clock for the essi. the sck0 is a clock input or output, used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes. although an external serial clock can be independent of and asynchronous to the dsp system clock, it must exceed the minimum clock cycle time of 6t (that is, the system clock frequency must be at least three times the external essi clock frequency). the essi needs at least three dsp phases inside each half of the serial clock. port c 3 ?the default configuration following reset is gpio input pc3. when configured as pc3, signal direction is controlled through the port c direction register. the signal can be configured as an essi signal sck0 through the port c control register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-14 enhanced synchronous serial interface 1 (essi1) 1.10 enhanced synchronous serial interface 1 (essi1) srd0 pc4 input input or output ignored input serial receive data ?receives serial data and transfers the data to the essi receive shift register. srd0 is an input when data is received. port c 4 ?the default configuration following reset is gpio input pc4. when configured as pc4, signal direction is controlled through the port c direction register. the signal can be configured as an essi signal srd0 through the port c control register. std0 pc5 output input or output ignored input serial transmit data ?transmits data from the serial transmit shift register. std0 is an output when data is transmitted. port c 5 ?the default configuration following reset is gpio input pc5. when configured as pc5, signal direction is controlled through the port c direction register. the signal can be configured as an essi signal std0 through the port c control register. notes: 1. in the stop state, the signal maintains the last state as follows: if the last state is input, the signal is an ignored input. if the last state is output, the signal is tri-stated. 2. the wait processing state does not affect the signal state. 3. all inputs are 5 v tolerant. table 1-13. enhanced serial synchronous interface 1 signal name type state during reset 1,2 signal description sc10 pd0 input or output input or output ignored input serial control 0 ?for asynchronous mode, this signal is used for the receive clock i/o (schmitt-trigger input). for synchronous mode, this signal is used either for transmitter 1 output or for serial i/o flag 0. port d 0 ?the default configuration following reset is gpio input pd0. when configured as pd0, signal direction is controlled through the port d direction register. the signal can be configured as an essi signal sc10 through the port d control register. sc11 pd1 input/output input or output ignored input serial control 1 ?for asynchronous mode, this signal is the receiver frame sync i/o. for synchronous mode, this signal is used either for transmitter 2 output or for serial i/o flag 1. port d 1 ?the default configuration following reset is gpio input pd1. when configured as pd1, signal direction is controlled through the port d direction register. the signal can be configured as an essi signal sc11 through the port d control register. table 1-12. enhanced synchronous serial interface 0 (continued) signal name type state during reset 1,2 signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-15 enhanced synchronous serial interface 1 (essi1) sc12 pd2 input/output input or output ignored input serial control signal 2 ?the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. when configured as an output, this signal is the internally generated frame sync signal. when configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). port d 2 ?the default configuration following reset is gpio input pd2. when configured as pd2, signal direction is controlled through the port d direction register. the signal can be configured as an essi signal sc12 through the port d control register. sck1 pd3 input/output input or output ignored input serial clock ?provides the serial bit rate clock for the essi. the sck1 is a clock input or output used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes. although an external serial clock can be independent of and asynchronous to the dsp system clock, it must exceed the minimum clock cycle time of 6t (that is, the system clock frequency must be at least three times the external essi clock frequency). the essi needs at least three dsp phases inside each half of the serial clock. port d 3 ?the default configuration following reset is gpio input pd3. when configured as pd3, signal direction is controlled through the port d direction register. the signal can be configured as an essi signal sck1 through the port d control register. srd1 pd4 input input or output ignored input serial receive data ?receives serial data and transfers the data to the essi receive shift register. srd1 is an input when data is being received. port d 4 ?the default configuration following reset is gpio input pd4. when configured as pd4, signal direction is controlled through the port d direction register. the signal can be configured as an essi signal srd1 through the port d control register. std1 pd5 output input or output ignored input serial transmit data ?transmits data from the serial transmit shift register. std1 is an output when data is being transmitted. port d 5 ?the default configuration following reset is gpio input pd5. when configured as pd5, signal direction is controlled through the port d direction register. the signal can be configured as an essi signal std1 through the port d control register. notes: 1. in the stop state, the signal maintains the last state as follows: if the last state is input, the signal is an ignored input. if the last state is output, the signal is tri-stated. 2. the wait processing state does not affect the signal state. 3. all inputs are 5 v tolerant. table 1-13. enhanced serial synchronous interface 1 (continued) signal name type state during reset 1,2 signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-16 serial communication interface (sci) 1.11 serial communication interface (sci) the sci provides a full duplex port for serial communication with other dsps, microprocessors, or peripherals such as modems. table 1-14. serial communication interface signal name type state during reset 1,2 signal description rxd pe0 input input or output ignored input serial receive data ?receives byte-oriented serial data and transfers it to the sci receive shift register. port e 0 ?the default configuration following reset is gpio input pe0. when configured as pe0, signal direction is controlled through the port e direction register. the signal can be configured as an sci signal rxd through the port e control register. txd pe1 output input or output ignored input serial transmit data ?transmits data from the sci transmit data register. port e 1 ?the default configuration following reset is gpio input pe1. when configured as pe1, signal direction is controlled through the port e direction register. the signal can be configured as an sci signal txd through the port e control register. sclk pe2 input/output input or output ignored input serial clock ?provides the input or output clock used by the transmitter and/or the receiver. port e 2 ?the default configuration following reset is gpio input pe2. when configured as pe2, signal direction is controlled through the port e direction register. the signal can be configured as an sci signal sclk through the port e control register. notes: 1. in the stop state, the signal maintains the last state as follows: if the last state is input, the signal is an ignored input. if the last state is output, the signal is tri-stated. 2. the wait processing state does not affect the signal state. 3. all inputs are 5 v tolerant. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-17 timers 1.12 timers the DSP56303 has three identical and independent timers. each timer can use internal or external clocking and can either interrupt the DSP56303 after a specified number of events (clocks) or signal an external device after counting a specific number of internal events. table 1-15. triple timer signals signal name type state during reset 1,2 signal description tio0 input or output ignored input timer 0 schmitt-trigger input/output ? when timer 0 functions as an external event counter or in measurement mode, tio0 is used as input. when timer 0 functions in watchdog, timer, or pulse modulation mode, tio0 is used as output. the default mode after reset is gpio input. tio0 can be changed to output or configured as a timer i/o through the timer 0 control/status register (tcsr0). tio1 input or output ignored input timer 1 schmitt-trigger input/output ? when timer 1 functions as an external event counter or in measurement mode, tio1 is used as input. when timer 1 functions in watchdog, timer, or pulse modulation mode, tio1 is used as output. the default mode after reset is gpio input. tio1 can be changed to output or configured as a timer i/o through the timer 1 control/status register (tcsr1). tio2 input or output ignored input timer 2 schmitt-trigger input/output ? when timer 2 functions as an external event counter or in measurement mode, tio2 is used as input. when timer 2 functions in watchdog, timer, or pulse modulation mode, tio2 is used as output. the default mode after reset is gpio input. tio2 can be changed to output or configured as a timer i/o through the timer 2 control/status register (tcsr2). notes: 1. in the stop state, the signal maintains the last state as follows: if the last state is input, the signal is an ignored input. if the last state is output, the signal is tri-stated. 2. the wait processing state does not affect the signal state. 3. all inputs are 5 v tolerant. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-18 jtag and once interface 1.13 jtag and once interface the dsp56300 family and in particular the DSP56303 support circuit-board test strategies based on the ieee 1149.1 standard test access port and boundary scan architecture , the industry standard developed under the sponsorship of the test technology committee of ieee and the jtag. the once module provides a means to interface nonintrusively with the dsp56300 core and its peripherals so that you can examine registers, memory, or on-chip peripherals. functions of the once module are provided through the jtag tap signals. for programming models, see the chapter on debugging support in the dsp56300 family manual . table 1-16. jtag/once interface signal name type state during reset signal description tck input input test clock ?a test clock input signal to synchronize the jtag test logic. tdi input input test data input ?a test data serial input signal for test instructions and data. tdi is sampled on the rising edge of tck and has an internal pull-up resistor. tdo output tri-stated test data output ?a test data serial output signal for test instructions and data. tdo is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tck. tms input input test mode select ?sequences the test controller?s state machine. tms is sampled on the rising edge of tck and has an internal pull-up resistor. trst input input test reset ?i nitializes the test controller asynchronously. trst has an internal pull-up resistor. trst must be asserted after powerup. de input/ output (open-drain) input debug event ?as an input, initiates debug mode from an external command controller, and, as an open-drain output, acknowledges that the chip has entered debug mode. as an input, de causes the dsp56300 core to finish executing the current instruction, save the instruction pipeline information, enter debug mode, and wait for commands to be entered from the debug serial input line. this signal is asserted as an output for three clock cycles when the chip enters debug mode as a result of a debug request or as a result of meeting a breakpoint condition. the de has an internal pull-up resistor. this signal is not a standard part of the jtag tap controller. the signal connects directly to the once module to initiate debug mode directly or to provide a direct external indication that the chip has entered debug mode. all other interface with the once module must occur through the jtag port. note: all inputs are 5 v tolerant. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-1 chapter 2 specifications 2.1 introduction the DSP56303 is fabricated in high-density cmos with transistor-transistor logic (ttl) compatible inputs and outputs. 2.2 maximum ratings note: in the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. a maximum specification is calculated using a worst case variation of process parameter values in one direction. the minimum specification is calculated using the worst case for the same parameters in the opposite direction. therefore, a ?maximum? value for a specification never occurs in the same device that has a ?minimum? value for another specification; adding a maximum to a minimum represents a condition that can never exist. caution this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either gnd or v cc ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-2 absolute maximum ratings 2.3 absolute maximum ratings 2.4 thermal characteristics table 2-1. absolute maximum ratings 1 rating symbol value unit supply voltage v cc ? 0.3 to +4.0 v all input voltages excluding ?5 v tolerant? inputs v in gnd ? 0.3 to v cc + 0.3 v all ?5 v tolerant? input voltages 2 v in5 gnd ? 0.3 to 5.5 v current drain per pin excluding v cc and gnd i 10 ma operating temperature range t j ? 40 to +100 c storage temperature t stg ? 55 to +150 c notes: 1. absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 2. at power-up, ensure that the voltage difference between the 5 v tolerant pins and the chip v cc never exceeds 3.5 v. table 2-2. thermal characteristics characteristic symbol tqfp value map-bga 3 value map-bga 4 value unit junction-to-ambient thermal resistance 1 r ja or ja 56 57 28 c/w junction-to-case thermal resistance 2 r jc or jc 11 15 ? c/w thermal characterization parameter jt 78? c/w notes: 1. junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per jedec specification jesd51-3. 2. junction-to-case thermal resistance is based on measurements using a cold plate per semi g30-88, with the exception that the cold plate temperature is used for the case temperature. 3. these are simulated values. see note 1 for test board conditions. 4. these are simulated values. the test board has two 2-ounce signal layers and two 1-ounce solid ground planes internal to the test board. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-3 dc electrical characteristics 2.5 dc electrical characteristics table 2-3. dc electrical characteristics 6 characteristics symbol min typ max unit supply voltage v cc 3.0 3.3 3.6 v input high voltage d[0?23], bg , bb , ta mod 1 /irq 1 , reset , pinit/nmi and all jtag/essi/sci/timer/hi08 pins extal 8 v ih v ihp v ihx 2.0 2.0 0.8 v cc ? ? ? v cc 5.25 v cc v v v input low voltage d[0?23], bg , bb , ta , mod 1 /irq 1 , reset , pinit all jtag/essi/sci/timer/hi08 pins extal 8 v il v ilp v ilx ?0.3 ?0.3 ?0.3 ? ? ? 0.8 0.8 0.2 v cc v v v input leakage current i in ?10 ? 10 a high impedance (off-state) input current (@ 2.4 v / 0.4 v) i tsi ?10 ? 10 a output high voltage ttl (i oh = ?0.4 ma) 5,7 cmos (i oh = ?10 a) 5 v oh 2.4 v cc ? 0.01 ? ? ? ? v v output low voltage ttl (i ol = 1.6 ma, open-drain pins i ol = 6.7 ma) 5,7 cmos (i ol = 10 a) 5 v ol ? ? ? ? 0.4 0.01 v v internal supply current 2 : in normal mode in wait mode 3 in stop mode 4 i cci i ccw i ccs ? ? ? 127 7.5 100 ? ? ? ma ma a pll supply current ? 1 2.5 ma input capacitance 5 c in ? ? 10 pf notes: 1. refers to moda/irqa , modb/irqb , modc/irqc , and modd/irqd pins. 2. section 4.3 provides a formula to compute the estimated current requirements in normal mode. in order to obtain these results, all inputs must be terminated (that is, not allowed to float). measurements are based on synthetic intensive dsp benchmarks (see appendix a ). the power consumption numbers in this specification are 90 percent of the measured results of this benchmark. this reflects typical dsp applications. typical internal supply current is measured with v cc = 3.3 v at t j = 100c. 3. in order to obtain these results, all inputs must be terminated (that is, not allowed to float). 4. in order to obtain these results, all inputs that are not disconnected at stop mode must be terminated (that is, not allowed to float). pll and xtal signals are disabled during stop state. 5. periodically sampled and not 100 percent tested. 6. v cc = 3.3 v 0.3 v; t j = ?40c to +100 c, c l = 50 pf 7. this characteristic does not apply to xtal and pcap. 8. driving extal to the low v ihx or the high v ilx value may cause additional power consumption (dc current). to minimize power consumption, the minimum v ihx should be no lower than 0.9 v cc and the maximum v ilx should be no higher than 0.1 v cc . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-4 ac electrical characteristics 2.6 ac electrical characteristics the timing waveforms shown in the ac electrical characteristics section are tested with a v il maximum of 0.3 v and a v ih minimum of 2.4 v for all pins except extal, which is tested using the input levels shown in note 6 of the previous table. ac timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50 percent point of the respective input signal transition. DSP56303 output levels are measured with the production test machine v ol and v oh reference levels set at 0.4 v and 2.4 v, respectively. note: although the minimum value for the frequency of extal is 0 mhz, the device ac test conditions are 15 mhz and rated speed. 2.6.1 internal clocks table 2-4. internal clocks, clkout characteristics symbol expression 1, 2 min typ max internal operation frequency and clkout with pll enabled f? (ef mf)/ (pdf df) ? internal operation frequency and clkout with pll disabled f ? ef/2 ? internal clock and clkout high period with pll disabled with pll enabled and mf 4 with pll enabled and mf > 4 t h ? 0.49 et c pdf df/mf 0.47 et c pdf df/mf et c ? ? ? 0.51 et c pdf df/mf 0.53 et c pdf df/mf internal clock and clkout low period with pll disabled with pll enabled and mf 4 with pll enabled and mf > 4 t l ? 0.49 et c pdf df/mf 0.47 et c pdf df/mf et c ? ? ? 0.51 et c pdf df/mf 0.53 et c pdf df/mf internal clock and clkout cycle time with pll enabled t c ?et c pdf df/mf ? internal clock and clkout cycle time with pll disabled t c ?2 et c ? instruction cycle time i cyc ?t c ? notes: 1. df = division factor; ef = external frequency; et c = external clock cycle; mf = multiplication factor; pdf = predivision factor; t c = internal clock cycle 2. see the pll and clock generation section in the dsp56300 family manual for a detailed discussion of the pll. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-5 ac electrical characteristics 2.6.2 external clock operation the DSP56303 system clock is derived from the on-chip oscillator or is externally supplied. to use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to extal and xtal; examples are shown in figure 2-1 . if an externally-supplied square wave voltage source is used, disable the internal oscillator circuit during bootup by setting xtld (pctl register bit 16 = 1?see the DSP56303 user?s manual ). the external square wave source connects to extal ; xtal is not physically connected to the board or socket. figure 2-2 shows the relationship between the extal input and the internal clock and clkout . figure 2-1. crystal oscillator circuits figure 2-2. external clock timing suggested component values: f osc = 4 mhz r = 680 k ? 10% c = 56 pf 20% calculations were done for a 4/20 mhz crystal with the following parameters: c l of 30/20 pf, c 0 of 7/6 pf, series resistance of 100/20 ? , and drive level of 2 mw. xtal1 c c r fundamental frequency crystal oscillator xtal extal f osc = 20 mhz r = 680 k ? 10% c = 22 pf 20% note: make sure that in the pctl register: xtld (bit 16) = 0 if f osc > 200 khz, xtlr (bit 15) = 0 extal v ilx v ihx midpoint note: the midpoint is 0.5 (v ihx + v ilx ). et h et l et c clkout with pll disabled clkout with pll enabled 7 5 7 6b 5 3 4 2 6a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-6 ac electrical characteristics 2.6.3 phase lock loop (pll) characteristics table 2-5. clock operation no. characteristics symbol 100 mhz min max 1 frequency of extal (extal pin frequency) the rise and fall time of this external clock should be 3 ns maximum. ef 0 100.0 2 extal input high 1, 2 with pll disabled (46.7%?53.3% duty cycle 6 ) with pll enabled (42.5%?57.5% duty cycle 6 ) et h 4.67 ns 4.25 ns 157.0 s 3 extal input low 1, 2 with pll disabled (46.7%?53.3% duty cycle 6 ) with pll enabled (42.5%?57.5% duty cycle 6 ) et l 4.67 ns 4.25 ns 157.0 s 4 extal cycle time 2 with pll disabled with pll enabled et c 10.00 ns 10.00 ns 273.1 s 5 internal clock change from extal fall with pll disabled 4.3 ns 11.0 ns 6 a.internal clock rising edge from extal rising edge with pll enabled (mf = 1 or 2 or 4, pdf = 1, ef > 15 mhz) 3,5 b. internal clock falling edge from extal falling edge with pll enabled (mf 4, pdf 1, ef / pdf > 15 mhz) 3,5 0.0 ns 0.0 ns 1.8 ns 1.8 ns 7 instruction cycle time = i cyc = t c 4 (see table 2-4 ) (46.7%?53.3% duty cycle) with pll disabled with pll enabled i cyc 20.0 ns 10.00 ns 8.53 s notes: 1. measured at 50 percent of the input transition. 2. the maximum value for pll enabled is given for minimum vco frequency (see table 2-4 ) and maximum mf. 3. periodically sampled and not 100 percent tested. 4. the maximum value for pll enabled is given for minimum vco frequency and maximum df. 5. the skew is not guaranteed for any other mf value. 6. the indicated duty cycle is for the specified maximum frequency for which a part is rated. the minimum clock high or low time required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. table 2-6. pll characteristics characteristics 100 mhz unit min max voltage controlled oscillator (vco) frequency when pll enabled (mf e f 2/pdf) 30 200 mhz pll external capacitor (pcap pin to v ccp ) (c pcap 1 ) @ mf 4 @ mf > 4 (580 mf) ? 100 830 mf (780 mf) ? 140 1470 mf pf pf note: c pcap is the value of the pll capacitor (connected between the pcap pin and v ccp ) computed using the appropriate expression listed above. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-7 ac electrical characteristics 2.6.4 reset, stop, mode select, and interrupt timing table 2-7. reset, stop, mode select, and interrupt timing 6 no. characteristics expression 100 mhz unit min max 8 delay from reset assertion to all pins at reset value 3 ??26.0ns 9 required reset duration 4 power on, external clock generator, pll disabled power on, external clock generator, pll enabled power on, internal oscillator during stop, xtal disabled (pctl bit 16 = 0) during stop, xtal enabled (pctl bit 16 = 1) during normal operation 50 et c 1000 et c 75000 et c 75000 et c 2.5 t c 2.5 t c 500.0 10.0 0.75 0.75 25.0 25.0 ? ? ? ? ? ? ns s ms ms ns ns 10 delay from asynchronous reset deassertion to first external address output (internal reset deassertion) 5 minimum maximum 3.25 t c + 2.0 20.25 t c + 10 34.5 ? ? 212.5 ns ns 11 synchronous reset set-up time from reset deassertion to clkout transition 1 minimum maximum t c 5.9 ? ? 10.0 ns ns 12 synchronous reset deasserted, delay time from the clkout transition 1 to the first external address output minimum maximum 3.25 t c + 1.0 20.25 t c + 1.0 33.5 ? ? 203.5 ns ns 13 mode select setup time 30.0 ? ns 14 mode select hold time 0.0 ? ns 15 minimum edge-triggered interrupt request assertion width 6.6 ? ns 16 minimum edge-triggered interrupt request deassertion width 6.6 ? ns 17 delay from irqa , irqb , irqc , irqd , nmi assertion to external memory access address out valid caused by first interrupt instruction fetch caused by first interrupt instruction execution 4.25 t c + 2.0 7.25 t c + 2.0 44.5 74.5 ? ? ns ns 18 delay from irqa , irqb , irqc , irqd , nmi assertion to general-purpose transfer output valid caused by first interrupt instruction execution 10 t c + 5.0 105.0 ? ns 19 delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts 1, 7, 8 (ws + 3.75) t c ? 10.94 ? note 8 ns 20 delay from rd assertion to interrupt request deassertion for level sensitive fast interrupts 1, 7, 8 (ws + 3.25) t c ? 10.94 ? note 8 ns 21 delay from wr assertion to interrupt request deassertion for level sensitive fast interrupts 1, 7, 8 dram for all ws sram ws = 1 sram ws = 2, 3 sram ws 4 (ws + 3.5) t c ? 10.94 (ws + 3.5) t c ? 10.94 (ws + 3) t c ? 10.94 (ws + 2.5) t c ? 10.94 ? ? ? ? note 8 note 8 note 8 note 8 ns ns ns ns 22 synchronous interrupt set-up time from irqa , irqb , irqc , irqd , nmi assertion to the clkout transition 2 5.9 t c ns 23 synchronous interrupt delay time from the clkout transition 2 to the first external address output valid caused by the first instruction fetch after coming out of wait processing state minimum maximum 8.25 t c + 1.0 24.75 t c + 5.0 83.5 ? ? 252.5 ns ns 24 duration for irqa assertion to recover from stop state 5.9 ? ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-8 ac electrical characteristics 25 delay from irqa assertion to fetch of first instruction (when exiting stop) 2, 3 pll is not active during stop (pctl bit 17 = 0) and stop delay is enabled (operating mode register bit 6 = 0) pll is not active during stop (pctl bit 17 = 0) and stop delay is not enabled (operating mode register bit 6 = 1) pll is active during stop (pctl bit 17 = 1) (implies no stop delay) plc et c pdf + (128 k ? plc/2) t c plc et c pdf + (23.75 0.5) t c (8.25 0.5) t c 1.3 232.5 ns 87.5 9.1 12.3 ms 97.5 ms ns 26 duration of level sensitive irqa assertion to ensure interrupt service (when exiting stop) 2, 3 pll is not active during stop (pctl bit 17 = 0) and stop delay is enabled (operating mode register bit 6 = 0) pll is not active during stop (pctl bit 17 = 0) and stop delay is not enabled (operating mode register bit 6 = 1) pll is active during stop (pctl bit 17 = 1) (implies no stop delay) plc et c pdf + (128k ? plc/2) t c plc et c pdf + (20.5 0.5) t c 5.5 t c 13.6 12.3 55.0 ? ? ? ms ms ns 27 interrupt requests rate hi08, essi, sci, timer dma irq , nmi (edge trigger) irq , nmi (level trigger) maximum: 12 t c 8 t c 8 t c 12 t c ? ? ? ? 120.0 80.0 80.0 120.0 ns ns ns ns 28 dma requests rate data read from hi08, essi, sci data write to hi08, essi, sci timer irq , nmi (edge trigger) maximum: 6 t c 7 t c 2 t c 3 t c ? ? ? ? 60.0 70.0 20.0 30.0 ns ns ns ns 29 delay from irqa , irqb , irqc , irqd , nmi assertion to external memory (dma source) access address out valid minimum: 4.25 t c + 2.0 30.3 ? ns table 2-7. reset, stop, mode select, and interrupt timing 6 (continued) no. characteristics expression 100 mhz unit min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-9 ac electrical characteristics notes: 1. when fast interrupts are used and irqa , irqb , irqc , and irqd are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. to avoid these timing restrictions, the deasserted edge-triggered mode is recommended when fast interrupts are used. long interrupts are recommended for level-sensitive mode. 2. this timing depends on several settings: for pll disable, using internal oscillator (pll control register (pctl) bit 16 = 0) and oscillator disabled during stop (pct l bit 17 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. resetting the stop delay (operating mode register bit 6 = 0) provides the proper delay. while operating mode register bit 6 = 1 can be set, it is not recommended, and these specifications do not guarantee timings for that case. for pll disable, using internal oscillator (pctl bit 16 = 0) and oscillator enabled during stop (pctl bit 17=1), no stabiliz ation delay is required and recovery is minimal (operating mode register bit 6 setting is ignored). for pll disable, using external clock (pctl bit 16 = 1), no stabilization delay is required and recovery time is defined by the pctl bit 17 and operating mode register bit 6 settings. for pll enable, if pctl bit 17 is 0, the pll is shutdown during stop. recovering from stop requires the pll to get locked. t he pll lock procedure duration, pll lock cycles (plc), may be in the range of 0 to 1000 cycles. this procedure occurs in parallel with the stop delay counter, and stop recovery ends when the last of these two events occurs. the stop delay counter completes count or pll lock procedure completion. plc value for pll disable is 0. the maximum value for et c is 4096 (maximum mf) divided by the desired internal frequency (that is, for 66 mhz it is 4096/66 mhz = 62 s). during the stabilization period, t c , t h, and t l is not constant, and their width may vary, so timing may vary as well. 3. periodically sampled and not 100 percent tested. 4. value depends on clock source: for an external clock generator, reset duration is measured while reset is asserted, v cc is valid, and the extal input is active and valid. for an internal oscillator, reset duration is measured while reset is asserted and v cc is valid. the specified timing reflects the crystal oscillator stabilization time after power-up. this number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. when the v cc is valid, but the other ?required reset duration? conditions (as specified above) have not been yet met, the device circuitry is in an uninitialized state that can result in significant power consumption and heat-up. designs should mini mize this state to the shortest possible duration. 5. if pll does not lose lock. 6. v cc = 3.3 v 0.3 v; t j = ?40c to +100c, c l = 50 pf. 7. ws = number of wait states (measured in clock cycles, number of t c ). 8. use the expression to compute a maximum value. figure 2-3. reset timing table 2-7. reset, stop, mode select, and interrupt timing 6 (continued) no. characteristics expression 100 mhz unit min max v ih reset reset value first fetch all pins a[0?17] 8 9 10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-10 ac electrical characteristics figure 2-4. synchronous reset timing figure 2-5. external fast interrupt timing clkout reset a[0?17] 11 12 a[0?17] rd a) first interrupt instruction execution general purpose i/o irqa , irqb , irqc , irqd , nmi b) general-purpose i/o irqa , irqb , irqc , irqd , nmi wr 20 21 19 17 18 first interrupt instruction execution/fetch f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-11 ac electrical characteristics figure 2-6. external interrupt timing (negative edge-triggered) figure 2-7. synchronous interrupt from wait state timing figure 2-8. operating mode select timing irqa , irqb , irqc , irqd , nmi irqa , irqb , irqc , irqd , nmi 15 16 clkout irqa , irqb , irqc , irqd , nmi a[0?17] 22 23 v ih v ih v il v ih v il 13 14 irqa , irqb , irqc , irqd , nmi reset moda, modb, modc, modd, pinit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-12 ac electrical characteristics figure 2-9. recovery from stop state using irqa figure 2-10. recovery from stop state using irqa interrupt service figure 2-11. external memory access (dma source) timing first instruction fetch irqa a[0?17] 24 25 irqa a[0?17] first irqa interrupt instruction fetch 26 25 29 dma source address first interrupt instruction execution a[0?17] rd wr irqa , irqb , irqc , irqd , nmi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-13 ac electrical characteristics 2.6.5 external memory expansion port (port a) 2.6.5.1 sram timing table 2-8. sram read and write accesses no. characteristics symbol expression 1 100 mhz unit min max 100 address valid and aa assertion pulse width 2 t rc , t wc (ws + 1) t c ? 4.0 [1 ws 3] (ws + 2) t c ? 4.0 [4 ws 7] (ws + 3) t c ? 4.0 [ws 8] 16.0 56.0 106.0 ? ? ? ns ns ns 101 address and aa valid to wr assertion t as 0.25 t c ? 2.0 [ws = 1] 0.75 t c ? 2.0 [2 ws 3] 1.25 t c ? 2.0 [ws 4] 0.5 5.5 10.5 ? ? ? ns ns ns 102 wr assertion pulse width t wp 1.5 t c ? 4.0 [ws = 1] ws t c ? 4.0 [2 ws 3] (ws ? 0.5) t c ? 4.0 [ws 4] 11.0 16.0 31.0 ? ? ? ns ns ns 103 wr deassertion to address not valid t wr 0.25 t c ? 2.0 [1 ws 3] 1.25 t c ? 4.0 [4 ws 7] 2.25 t c ? 4.0 [ws 8] 0.5 8.5 18.5 ? ? ? ns ns ns 104 address and aa valid to input data valid t aa , t ac (ws + 0.75 ) t c ? 5.0 [ws 1] ?12.5ns 105 rd assertion to input data valid t oe (ws + 0.25) t c ? 5.0 [ws 1] ?7.5ns 106 rd deassertion to data not valid (data hold time) t ohz 0.0 ? ns 107 address valid to wr deassertion 2 t aw (ws + 0.75) t c ? 4.0 [ws 1] 13.5 ? ns 108 data valid to wr deassertion (data setup time) t ds (t dw )(ws ? 0.25) t c ? 3.0 [ws 1] 4.5 ? ns 109 data hold time from wr deassertion t dh 0.25 t c ? 2.0 [1 ws 3] 1.25 t c ? 2.0 [4 ws 7] 2.25 t c ? 2.0 [ws 8] 0.5 10.5 20.5 ? ? ? ns ns ns 110 wr assertion to data active ? 0.75 t c ? 3.7 [ws = 1] 0.25 t c ? 3.7 [2 ws 3] ? 0.25 t c ? 3.7 [ws 4] 3.8 ?1.2 ?6.2 ? ? ? ns ns ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-14 ac electrical characteristics 111 wr deassertion to data high impedance ? 0.25 t c + 0.2 [1 ws 3] 1.25 tc + 0.2 [4 ws 7] 2.25 t c + 0.2 [ws > 8] ? ? ? 2.7 12.7 22.7 ns ns ns 112 previous rd deassertion to data active (write) ? 1.25 t c ? 4.0 [1 ws 3] 2.25 t c ? 4.0 [4 ws 7] 3.25 t c ? 4.0 [ws > 8] 8.5 18.5 28.5 ? ? ? ns ns ns 113 rd deassertion time ? 0.75 t c ? 4.0 [1 ws 3] 1.75 t c ? 4.0 [4 ws 7] 2.75 t c ? 4.0 [ws 8] 3.5 13.5 23.5 ? ? ? ns ns ns 114 wr deassertion time ? 0.5 t c ? 4.0 [ws = 1] t c ? 4.0 [2 ws 3] 2.5 t c ? 4.0 [4 ws 7] 3.5 t c ? 4.0 [ws 8] 1.0 6.0 21.0 31.0 ? ? ? ? ns ns ns ns 115 address valid to rd assertion ? 0.5 t c ? 4.0 1.0 ? ns 116 rd assertion pulse width ? (ws + 0.25) t c ? 4.0 8.5 ? ns 117 rd deassertion to address not valid ? 0.25 t c ? 2 .0 [1 ws 3] 1.25 t c ? 2.0 [4 ws 7] 2.25 t c ? 2.0 [ws 8] 0.5 10.5 20.5 ? ? ? ns ns ns 118 ta setup before rd or wr deassertion 4 ?0.25 t c + 2.0 4.5 ? ns 119 ta hold after rd or wr deassertion ? ? 0 ? ns notes: 1. ws is the number of wait states specified in the bcr. an expression is used to compute the number listed as the minimum or maximum value, as appropriate. 2. timings 100, 107 are guaranteed by design, not tested. 3. all timings for 100 mhz are measured from 0.5 vcc to 0.5 vcc. 4. timing 118 is relative to the deassertion edge of rd or wr even if ta remains asserted. 5. v cc = 3.3 v 0.3 v; t j = ?40c to +100c, c l = 50 pf table 2-8. sram read and write accesses (continued) no. characteristics symbol expression 1 100 mhz unit min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-15 ac electrical characteristics figure 2-12. sram read access figure 2-13. sram write access a[0?17] rd wr d[0?23] aa[0?3] 105 106 113 104 116 117 100 ta 118 data in 119 note: address lines a[0?17] hold their state after a read or write operation. aa[0?3] do not hold their state after a read or write operation. a[0?17] wr rd data out d[0?23] aa[0?3] 100 102 101 107 114 108 109 103 ta 118 119 note: address lines a[0?17] hold their state after a read or write operation. aa[0?3] do not hold their state after a read or write operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-16 ac electrical characteristics 2.6.5.2 dram timing the selection guides in figure 2-14 and figure 2-17 are for primary selection only. final selection should be based on the timing in the following tables. for example, the selection guide suggests that four wait states must be used for 100 mhz operation with page mode dram. however, consulting the appropriate table, a designer can evaluate whether fewer wait states might suffice by determining which timing prevents operation at 100 mhz, running the chip at a slightly lower frequency (for example, 95 mhz), using faster dram (if it becomes available), and manipulating control factors such as capacitive and resistive load to improve overall system performance. figure 2-14. dram page mode wait state selection guide chip frequency (mhz) dram type (trac ns) 100 80 70 60 40 66 80 100 1 wait states 2 wait states 3 wait states 4 wait states note: this figure should be used for primary selection. for exact and detailed timings, see the following tables. 50 120 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-17 ac electrical characteristics table 2-9. dram page mode timings, three wait states 1,2,3 no. characteristics symbol expression 4 100 mhz unit min max 131 page mode cycle time for two consecutive accesses of the same direction page mode cycle time for mixed (read and write) accesses t pc 4 t c 3.5 t c 40.0 35.0 ? ? ns ns 132 cas assertion to data valid (read) t cac 2 t c ? 5.7 ? 14.3 ns 133 column address valid to data valid (read) t aa 3 t c ? 5.7 ? 24.3 ns 134 cas deassertion to data not valid (read hold time) t off 0.0 ? ns 135 last cas assertion to ras deassertion t rsh 2.5 t c ? 4.0 21.0 ? ns 136 previous cas deassertion to ras deassertion t rhcp 4.5 t c ? 4.0 41.0 ? ns 137 cas assertion pulse width t cas 2 t c ? 4.0 16.0 ? ns 138 last cas deassertion to ras assertion 5 brw[1?0] = 00, 01?not applicable brw[1?0] = 10 brw[1?0] = 11 t crp ? 4.75 t c ? 6.0 6.75 t c ? 6.0 ? 41.5 61.5 ? ? ? ? ns ns 139 cas deassertion pulse width t cp 1.5 t c ? 4.0 11.0 ? ns 140 column address valid to cas assertion t asc t c ? 4.0 6.0 ? ns 141 cas assertion to column address not valid t cah 2.5 t c ? 4.0 21.0 ? ns 142 last column address valid to ras deassertion t ral 4 t c ? 4.0 36.0 ? ns 143 wr deassertion to cas assertion t rcs 1.25 t c ? 4.0 8.5 ? ns 144 cas deassertion to wr assertion t rch 0.75 t c ? 4.0 3.5 ? ns 145 cas assertion to wr deassertion t wch 2.25 t c ? 4.2 18.3 ? ns 146 wr assertion pulse width t wp 3.5 t c ? 4.5 30.5 ? ns 147 last wr assertion to ras deassertion t rwl 3.75 t c ? 4.3 33.2 ? ns 148 wr assertion to cas deassertion t cwl 3.25 t c ? 4.3 28.2 ? ns 149 data valid to cas assertion (write) t ds 0.5 t c ? 4.5 0.5 ? ns 150 cas assertion to data not valid (write) t dh 2.5 t c ? 4.0 21.0 ? ns 151 wr assertion to cas assertion t wcs 1.25 t c ? 4.3 8.2 ? ns 152 last rd assertion to ras deassertion t roh 3.5 t c ? 4.0 31.0 ? ns 153 rd assertion to data valid t ga 2.5 t c ? 5.7 ? 19.3 ns 154 rd deassertion to data not valid 6 t gz 0.0 ? ns 155 wr assertion to data active 0.75 t c ? 1.5 6.0 ? ns 156 wr deassertion to data high impedance 0.25 t c ?2.5ns notes: 1. the number of wait states for page mode access is specified in the dram control register. 2. the refresh period is specified in the dram control register. 3. the asynchronous delays specified in the expressions are valid for the DSP56303 . 4. all the timings are calculated for the worst case. some of the timings are better for specific cases (for example, t pc equals 4 t c for read-after-read or write-after-write sequences). an expression is used to compute the number listed as the minimum or maximum value listed, as appropriate. 5. brw[1?0] (dram control register bits) defines the number of wait states that should be inserted in each dram out-of page-access. 6. rd deassertion always occurs after cas deassertion; therefore, the restricted timing is t off and not t gz . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-18 ac electrical characteristics table 2-10. dram page mode timings, four wait states 1,2,3 no. characteristics symbol expression 4 100 mhz unit min max 131 page mode cycle time for two consecutive accesses of the same direction page mode cycle time for mixed (read and write) accesses t pc 5 t c 4.5 t c 50.0 45.0 ? ? ns ns 132 cas assertion to data valid (read) t cac 2.75 t c ? 5.7 ? 21.8 ns 133 column address valid to data valid (read) t aa 3.75 t c ? 5.7 ? 31.8 ns 134 cas deassertion to data not valid (read hold time) t off 0.0 ? ns 135 last cas assertion to ras deassertion t rsh 3.5 t c ? 4.0 31.0 ? ns 136 previous cas deassertion to ras deassertion t rhcp 6 t c ? 4.0 56.0 ? ns 137 cas assertion pulse width t cas 2.5 t c ? 4.0 21.0 ? ns 138 last cas deassertion to ras assertion 5 brw[1?0] = 00, 01?not applicable brw[1?0] = 10 brw[1?0] = 11 t crp ? 5.25 t c ? 6.0 7.25 t c ? 6.0 ? 46.5 66.5 ? ? ? ? ns ns 139 cas deassertion pulse width t cp 2 t c ? 4.0 16.0 ? ns 140 column address valid to cas assertion t asc t c ? 4.0 6.0 ? ns 141 cas assertion to column address not valid t cah 3.5 t c ? 4.0 31.0 ? ns 142 last column address valid to ras deassertion t ral 5 t c ? 4.0 46.0 ? ns 143 wr deassertion to cas assertion t rcs 1.25 t c ? 4.0 8.5 ? ns 144 cas deassertion to wr assertion t rch 1.25 t c ? 3.7 8.8 ? ns 145 cas assertion to wr deassertion t wch 3.25 t c ? 4.2 28.3 ? ns 146 wr assertion pulse width t wp 4.5 t c ? 4.5 40.5 ? ns 147 last wr assertion to ras deassertion t rwl 4.75 t c ? 4.3 43.2 ? ns 148 wr assertion to cas deassertion t cwl 3.75 t c ? 4.3 33.2 ? ns 149 data valid to cas assertion (write) t ds 0.5 t c ? 4.5 0.5 ? ns 150 cas assertion to data not valid (write) t dh 3.5 t c ? 4.0 31.0 ? ns 151 wr assertion to cas assertion t wcs 1.25 t c ? 4.3 8.2 ? ns 152 last rd assertion to ras deassertion t roh 4.5 t c ? 4.0 41.0 ? ns 153 rd assertion to data valid t ga 3.25 t c ? 5.7 ? 26.8 ns 154 rd deassertion to data not valid 6 t gz 0.0 ? ns 155 wr assertion to data active 0.75 t c ? 1.5 6.0 ? ns 156 wr deassertion to data high impedance 0.25 t c ?2.5ns notes: 1. the number of wait states for page mode access is specified in the dram control register. 2. the refresh period is specified in the dram control register. 3. the asynchronous delays specified in the expressions are valid for the DSP56303. 4. all the timings are calculated for the worst case. some of the timings are better for specific cases (for example, t pc equals 3 t c for read-after-read or write-after-write sequences). an expressions is used to calculate the maximum or minimum value listed, as appropriate. 5. brw[1?0] (dram control register bits) defines the number of wait states that should be inserted in each dram out-of-page access. 6. rd deassertion always occurs after cas deassertion; therefore, the restricted timing is t off and not t gz . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-19 ac electrical characteristics figure 2-15. dram page mode write accesses figure 2-16. dram page mode read accesses ras cas a[0?17] wr rd d[0?23] column row data out data out data out last column column add address address address 136 135 131 139 141 137 140 142 147 144 151 148 146 155 156 150 138 145 149 ras cas a[0?17] wr rd d[0?23] column last column column row data in data in data in add address address address 136 135 131 137 140 141 142 143 152 133 153 132 138 139 134 154 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-20 ac electrical characteristics figure 2-17. dram out-of-page wait state selection guide table 2-11. dram out-of-page and refresh timings, eleven wait states 1,2 no. characteristics symbol expression 3 100 mhz unit min max 157 random read or write cycle time t rc 12 t c 120.0 ? ns 158 ras assertion to data valid (read) t rac 6.25 t c ? 7.0 ? 55.5 ns 159 cas assertion to data valid (read) t cac 3.75 t c ? 7.0 ? 30.5 ns 160 column address valid to data valid (read) t aa 4.5 t c ? 7.0 ? 38.0 ns 161 cas deassertion to data not valid (read hold time) t off 0.0 ? ns 162 ras deassertion to ras assertion t rp 4.25 t c ? 4.0 38.5 ? ns 163 ras assertion pulse width t ras 7.75 t c ? 4.0 73.5 ? ns 164 cas assertion to ras deassertion t rsh 5.25 t c ? 4.0 48.5 ? ns 165 ras assertion to cas deassertion t csh 6.25 t c ? 4.0 58.5 ? ns 166 cas assertion pulse width t cas 3.75 t c ? 4.0 33.5 ? ns 167 ras assertion to cas assertion t rcd 2.5 t c 4.0 21.0 29.0 ns 168 ras assertion to column address valid t rad 1.75 t c 4.0 13.5 21.5 ns 169 cas deassertion to ras assertion t crp 5.75 t c ? 4.0 53.5 ? ns 170 cas deassertion pulse width t cp 4.25 t c ? 6.0 36.5 ? ns chip frequency (mhz) dram type (trac ns) 100 80 70 50 66 80 100 4 wait states 8 wait states 11 wait states 15 wait states note: this figure should be used for primary selection. for exact and detailed timings, see the following tables. 60 40 120 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-21 ac electrical characteristics 171 row address valid to ras assertion t asr 4.25 t c ? 4.0 38.5 ? ns 172 ras assertion to row address not valid t rah 1.75 t c ? 4.0 13.5 ? ns 173 column address valid to cas assertion t asc 0.75 t c ? 4.0 3.5 ? ns 174 cas assertion to column address not valid t cah 5.25 t c ? 4.0 48.5 ? ns 175 ras assertion to column address not valid t ar 7.75 t c ? 4.0 73.5 ? ns 176 column address valid to ras deassertion t ral 6 t c ? 4.0 56.0 ? ns 177 wr deassertion to cas assertion t rcs 3.0 t c ? 4.0 26.0 ? ns 178 cas deassertion to wr 4 assertion t rch 1.75 t c ? 3.7 13.8 ? ns 179 ras deassertion to wr 4 assertion t rrh 0.25 t c ? 2.0 0.5 ? ns 180 cas assertion to wr deassertion t wch 5 t c ? 4.2 45.8 ? ns 181 ras assertion to wr deassertion t wcr 7.5 t c ? 4.2 70.8 ? ns 182 wr assertion pulse width t wp 11.5 t c ? 4.5 110.5 ? ns 183 wr assertion to ras deassertion t rwl 11.75 t c ? 4.3 113.2 ? ns 184 wr assertion to cas deassertion t cwl 10.25 t c ? 4.3 98.2 ? ns 185 data valid to cas assertion (write) t ds 5.75 t c ? 4.0 53.5 ? ns 186 cas assertion to data not valid (write) t dh 5.25 t c ? 4.0 48.5 ? ns 187 ras assertion to data not valid (write) t dhr 7.75 t c ? 4.0 73.5 ? ns 188 wr assertion to cas assertion t wcs 6.5 t c ? 4.3 60.7 ? ns 189 cas assertion to ras assertion (refresh) t csr 1.5 t c ? 4.0 11.0 ? ns 190 ras deassertion to cas assertion (refresh) t rpc 2.75 t c ? 4.0 23.5 ? ns 191 rd assertion to ras deassertion t roh 11.5 t c ? 4.0 111.0 ? ns 192 rd assertion to data valid t ga 10 t c ? 7.0 ? 93.0 ns 193 rd deassertion to data not valid 5 t gz 0.0 ? ns 194 wr assertion to data active 0.75 t c ? 1.5 6.0 ? ns 195 wr deassertion to data high impedance 0.25 t c ?2.5ns notes: 1. the number of wait states for an out-of-page access is specified in the dram control register. 2. the refresh period is specified in the dram control register. 3. use the expression to compute the maximum or minimum value listed (or both if the expression includes ) . 4. either t rch or t rrh must be satisfied for read cycles. 5. rd deassertion always occurs after cas deassertion; therefore, the restricted timing is t off and not t gz . ta ble 2 -11. dram out-of-page and refresh timings, eleven wait states 1,2 (continued) no. characteristics symbol expression 3 100 mhz unit min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-22 ac electrical characteristics table 2-12. dram out-of-page and refresh timings, fifteen wait states 1,2 no. characteristics symbol expression 3 100 mhz unit min max 157 random read or write cycle time t rc 16 t c 160.0 ? ns 158 ras assertion to data valid (read) t rac 8.25 t c ? 5.7 ? 76.8 ns 159 cas assertion to data valid (read) t cac 4.75 t c ? 5.7 ? 41.8 ns 160 column address valid to data valid (read) t aa 5.5 t c ? 5.7 ? 49.3 ns 161 cas deassertion to data not valid (read hold time) t off 0.0 0.0 ? ns 162 ras deassertion to ras assertion t rp 6.25 t c ? 4.0 58.5 ? ns 163 ras assertion pulse width t ras 9.75 t c ? 4.0 93.5 ? ns 164 cas assertion to ras deassertion t rsh 6.25 t c ? 4.0 58.5 ? ns 165 ras assertion to cas deassertion t csh 8.25 t c ? 4.0 78.5 ? ns 166 cas assertion pulse width t cas 4.75 t c ? 4.0 43.5 ? ns 167 ras assertion to cas assertion t rcd 3.5 t c 2 33.0 37.0 ns 168 ras assertion to column address valid t rad 2.75 t c 2 25.5 29.5 ns 169 cas deassertion to ras assertion t crp 7.75 t c ? 4.0 73.5 ? ns 170 cas deassertion pulse width t cp 6.25 t c ? 6.0 56.5 ? ns 171 row address valid to ras assertion t asr 6.25 t c ? 4.0 58.5 ? ns 172 ras assertion to row address not valid t rah 2.75 t c ? 4.0 23.5 ? ns 173 column address valid to cas assertion t asc 0.75 t c ? 4.0 3.5 ? ns 174 cas assertion to column address not valid t cah 6.25 t c ? 4.0 58.5 ? ns 175 ras assertion to column address not valid t ar 9.75 t c ? 4.0 93.5 ? ns 176 column address valid to ras deassertion t ral 7 t c ? 4.0 66.0 ? ns 177 wr deassertion to cas assertion t rcs 5 t c ? 3.8 46.2 ? ns 178 cas deassertion to wr 4 assertion t rch 1.75 t c ? 3.7 13.8 ? ns 179 ras deassertion to wr 4 assertion t rrh 0.25 t c ? 2.0 0.5 ? ns 180 cas assertion to wr deassertion t wch 6 t c ? 4.2 55.8 ? ns 181 ras assertion to wr deassertion t wcr 9.5 t c ? 4.2 90.8 ? ns 182 wr assertion pulse width t wp 15.5 t c ? 4.5 150.5 ? ns 183 wr assertion to ras deassertion t rwl 15.75 t c ? 4.3 153.2 ? ns 184 wr assertion to cas deassertion t cwl 14.25 t c ? 4.3 138.2 ? ns 185 data valid to cas assertion (write) t ds 8.75 t c ? 4.0 83.5 ? ns 186 cas assertion to data not valid (write) t dh 6.25 t c ? 4.0 58.5 ? ns 187 ras assertion to data not valid (write) t dhr 9.75 t c ? 4.0 93.5 ? ns 188 wr assertion to cas assertion t wcs 9.5 t c ? 4.3 90.7 ? ns 189 cas assertion to ras assertion (refresh) t csr 1.5 t c ? 4.0 11.0 ? ns 190 ras deassertion to cas assertion (refresh) t rpc 4.75 t c ? 4.0 43.5 ? ns 191 rd assertion to ras deassertion t roh 15.5 t c ? 4.0 151.0 ? ns 192 rd assertion to data valid t ga 14 t c ? 5.7 ? 134.3 ns 193 rd deassertion to data not valid 5 t gz 0.0 ? ns 194 wr assertion to data active 0.75 t c ? 1.5 6.0 ? ns 195 wr deassertion to data high impedance 0.25 t c ?2.5ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-23 ac electrical characteristics notes: 1. the number of wait states for an out-of-page access is specified in the dram control register. 2. the refresh period is specified in the dram control register. 3. use the expression to compute the maximum or minimum value listed (or both if the expression includes ) . 4. either t rch or t rrh must be satisfied for read cycles. 5. rd deassertion always occurs after cas deassertion; therefore, the restricted timing is t off and not t gz . figure 2-18. dram out-of-page read access table 2-12. dram out-of-page and refresh timings, fifteen wait states 1,2 (continued) no. characteristics symbol expression 3 100 mhz unit min max ras cas a[0?17] wr rd d[0?23] data row address column address in 157 163 165 162 162 169 170 171 168 167 164 166 173 174 175 172 177 176 191 160 178 159 193 161 192 158 179 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-24 ac electrical characteristics figure 2-19. dram out-of-page write access figure 2-20. dram refresh access ras cas a[0?17] wr rd d[0?23] data out column address row address 162 163 165 162 157 169 170 167 168 164 166 171 173 174 176 172 181 175 180 188 182 184 183 187 185 194 186 195 ras cas wr 157 163 162 162 190 170 165 189 177 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-25 ac electrical characteristics 2.6.5.3 synchronous timings table 2-13. external bus synchronous timings 1,2 no. characteristics expression 3,4,5 100 mhz unit min max 198 clkout high to address, and aa valid 6 0.25 t c + 4.0 ? 6.5 ns 199 clkout high to address, and aa invalid 6 0.25 t c 2.5 ? ns 200 ta valid to clkout high (set-up time) 4.0 ? ns 201 clkout high to ta invalid (hold time) 0.0 ? ns 202 clkout high to data out active 0.25 t c 2.5 ? ns 203 clkout high to data out valid 0.25 t c + 4.0 ? 6.5 ns 204 clkout high to data out invalid 0.25 t c 2.5 ? ns 205 clkout high to data out high impedance 0.25 t c ?2.5 ns 206 data in valid to clkout high (set-up) 4.0 ? ns 207 clkout high to data in invalid (hold) 0.0 ? ns 208 clkout high to rd assertion maximum: 0.75 t c + 2.5 6.7 10.0 ns 209 clkout high to rd deassertion 0.0 4.0 ns 210 clkout high to wr assertion 2 maximum: 0.5 t c + 4.3 for ws = 1 or ws 4 for 2 ws 3 5.0 0.0 9.3 4.3 ns ns 211 clkout high to wr deassertion 0.0 3.8 ns notes: 1. use external bus synchronous timings only for reference to the clock and not for relative timings. 2. synchronous bus arbitration is not recommended. use asynchronous mode whenever possible. 3. ws is the number of wait states specified in the bcr. 4. if ws > 1, wr assertion refers to the next rising edge of clkout. 5. use the expression to compute the maximum or minimum value listed, as appropriate. for timing 210, the minimum is an absolute value. 6. t198 and t199 are valid for address trace mode if the ate bit in the operating mode register is set. when this mode is enabled, use the status of br (see t212) to determine whether the access referenced by a[0?17] is internal or external. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-26 ac electrical characteristics figure 2-21. synchronous bus timings 1 ws (bcr controlled) figure 2-22. synchronous bus timings 2 ws (ta controlled) wr rd data out d[0?23] clkout ta data in d[0?23] a[0?17] aa[0?3] 199 201 2 00 211 210 208 209 207 198 205 204 203 202 206 note : address lines a[0?17] hold their state after a read or write operation. aa[0?3] do not hold their state after a read or write operation. a[0?17] wr rd data out d[0?23] aa[0?3] clkout ta data in d[0?23] 198 199 201 200 201 211 209 207 208 210 200 203 202 205 204 206 note : address lines a[0?17] hold their state after a read or write operation. aa[0?3] do not hold their state after a read or write operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-27 ac electrical characteristics 2.6.5.4 arbitration timings table 2-14. arbitration bus timings 1 no. characteristics expression 2 100 mhz unit min max 212 clkout high to br assertion/deassertion 3 0.0 4.0 ns 213 bg asserted/deasserted to clkout high (setup) 4.0 ? ns 214 clkout high to bg deasserted/asserted (hold) 0.0 ? ns 215 bb deassertion to clkout high (input set-up) 4.0 ? ns 216 clkout high to bb assertion (input hold) 0.0 ? ns 217 clkout high to bb assertion (output) 0.0 4.0 ns 218 clkout high to bb deassertion (output) 0.0 4.0 ns 219 bb high to bb high impedance (output) ? 4.5 ns 220 clkout high to address and controls active 0.25 t c 2.5 ? ns 221 clkout high to address and controls high impedance 0.75 t c ?7.5 ns 222 clkout high to aa active 0.25 t c 2.5 ? ns 223 clkout high to aa deassertion maximum: 0.25 t c + 4.02.06.5ns 224 clkout high to aa high impedance 0.75 t c ?7.5 ns notes: 1. synchronous bus arbitration is not recommended. use asynchronous mode whenever possible. 2. an expression is used to compute the maximum or minimum value listed, as appropriate. for timing 223, the minimum is an absolute value. 3. t212 is valid for address trace mode when the ate bit in the operating mode register is set. br is deasserted for internal accesses and asserted for external accesses. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-28 ac electrical characteristics figure 2-23. bus acquisition timings figure 2-24. bus release timings case 1 (brt bit in operating mode register cleared) a[0?17] bb aa[0?3] clkout br bg rd , wr 212 214 216 215 220 217 213 222 note : address lines a[0?17] hold their state after a read or write operation. aa[0?3] do not hold their state after a read or write operation. a[0?17] bb aa[0?3] clkout br bg rd , wr 212 214 218 221 224 223 213 219 note: address lines a[0?17] hold their state after a read or write operation. aa[0?3] do not hold their state after a read or write operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-29 ac electrical characteristics figure 2-25. bus release timings case 2 (brt bit in operating mode register set) a[0?17] bb aa[0?3] clkout br bg rd , wr 223 218 219 214 212 213 221 224 note: address lines a[0?17] hold their state after a read or write operation. aa[0?3] do not hold their state after a read or write operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-30 ac electrical characteristics 2.6.5.5 asynchronous bus arbitration timings the asynchronous bus arbitration is enabled by internal synchronization circuits on bg and bb inputs. these synchronization circuits add delay from the external signal until it is exposed to internal logic. as a result of this delay, a dsp56300 part may assume mastership and assert bb , for some time after bg is deasserted. this is the reason for timing 250. once bb is asserted, there is a synchronization delay from bb assertion to the time this assertion is exposed to other dsp56300 components that are potential masters on the same bus. if bg input is asserted before that time, and bg is asserted and bb is deasserted, another dsp56300 component may assume mastership at the same time. therefore, some non-overlap period between one bg input active to another bg input active is required. timing 251 ensures that overlaps are avoided. table 2-15. asynchronous bus timings 1, 2 no. characteristics expression 3 100 mhz 4 unit min max 250 bb assertion window from bg input deassertion 5 2.5 tc + 5 ? 30 ns 251 delay from bb assertion to bg assertion 5 2 tc + 5 25 ? ns notes: 1. bit 13 in the operating mode register must be set to enter asynchronous arbitration mode. 2. if asynchronous arbitration mode is active, none of the timings in table 2-14 is required. 3. an expression is used to compute the maximum or minimum value listed, as appropriate. 4. asynchronous arbitration mode is recommended for operation at 100 mhz. 5. in order to guarantee timings 250, and 251, bg inputs must be asserted to different dsp56300 devices on the same bus in the non-overlap manner shown in figure 2-26 . figure 2-26. asynchronous bus arbitration timing bg1 bb 251 bg2 250 250+251 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-31 ac electrical characteristics 2.6.6 host interface timing table 2-16. host interface timings 1,2,12 no. characteristic 10 expression 100 mhz unit min max 317 read data strobe assertion width 5 hack assertion width t c + 9.9 19.9 ? ns 318 read data strobe deassertion width 5 hack deassertion width 9.9 ? ns 319 read data strobe deassertion width 5 after ?last data register? reads 8,11 , or between two consecutive cvr, icr, or isr reads 3 hack deassertion width after ?last data register? reads 8,11 2.5 t c + 6.6 31.6 ? ns 320 write data strobe assertion width 6 13.2 ?ns 321 write data strobe deassertion width 8 hack write deassertion width after icr, cvr and ?last data register? writes after ivr writes, or after txh:txm:txl writes (with hlend= 0), or after txl:txm:txh writes (with hlend = 1) 2.5 t c + 6.6 31.8 16.5 ? ? ns ns 322 has assertion width 9.9 ? ns 323 has deassertion to data strobe assertion 4 0.0 ? ns 324 host data input setup time before write data strobe deassertion 6 9.9 ? ns 325 host data input hold time after write data strobe deassertion 6 3.3 ? ns 326 read data strobe assertion to output data active from high impedance 5 hack assertion to output data active from high impedance 3.3 ? ns 327 read data strobe assertion to output data valid 5 hack assertion to output data valid ?24.5ns 328 read data strobe deassertion to output data high impedance 5 hack deassertion to output data high impedance ?9.9ns 329 output data hold time after read data strobe deassertion 5 output data hold time after hack deassertion 3.3 ? ns 330 hcs assertion to read data strobe deassertion 5 t c + 9.9 19.9 ? ns 331 hcs assertion to write data strobe deassertion 6 9.9 ? ns 332 hcs assertion to output data valid ? 19.3 ns 333 hcs hold time after data strobe deassertion 4 0.0 ? ns 334 address (had[0?7]) setup time before has deassertion (hmux=1) 4.6 ? ns 335 address (had[0?7]) hold time after has deassertion (hmux=1) 3.3 ? ns 336 ha[8?10] (hmux=1), ha[0?2] (hmux=0), hr/w setup time before data strobe assertion 4 read write 0 4.6 ? ? ns ns 337 ha[8?10] (hmux=1), ha[0?2] (hmux=0), hr/w hold time after data strobe deassertion 4 3.3 ? ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-32 ac electrical characteristics 338 delay from read data strobe deassertion to host request assertion for ?last data register? read 5, 7, 8 t c + 5.3 15.3 ? ns 339 delay from write data strobe deassertion to host request assertion for ?last data register? write 6, 7, 8 1.5 t c + 5.3 20.3 ? ns 340 delay from data strobe assertion to host request deassertion for ?last data register? read or write (hrod=0) 4, 7, 8 ?19.3ns 341 delay from data strobe assertion to host request deassertion for ?last data register? read or write (hrod=1, open drain host request) 4, 7, 8, 9 ? 300.0 ns notes: 1. see the programmer?s model section in the chapter on the hi08 in the DSP56303user?s manual . 2. in the timing diagrams below, the controls pins are drawn as active low. the pin polarity is programmable. 3. this timing is applicable only if two consecutive reads from one of these registers are executed. 4. the data strobe is host read (hrd) or host write (hwr) in the dual data strobe mode and host data strobe (hds) in the single data strobe mode. 5. the read data strobe is hrd in the dual data strobe mode and hds in the single data strobe mode. 6. the write data strobe is hwr in the dual data strobe mode and hds in the single data strobe mode. 7. the host request is hreq in the single host request mode and hrrq and htrq in the double host request mode. 8. the ?last data register? is the register at address $7, which is the last location to be read or written in data transfers. this is rxl/txl in the big endian mode (hlend = 0; hlend is the interface control register bit 7?icr[7]), or rxh/txh in the little endian mode (hlend = 1). 9. in this calculation, the host request signal is pulled up by a 4.7 k ? resistor in the open-drain mode. 10. v cc = 3.3 v 0.3 v; t j = ?40c to +100 c, c l = 50 pf 11. this timing is applicable only if a read from the ?last data register? is followed by a read from the rxl, rxm, or rxh registers without first polling rxdf or hreq bits, or waiting for the assertion of the hreq signal. 12. after the external host writes a new value to the icr, the hi08 is ready for operation after three dsp clock cycles (3 tc). figure 2-27. host interrupt vector register (ivr) read timing diagram table 2-16. host interface timings 1,2,12 (continued) no. characteristic 10 expression 100 mhz unit min max hack h[0?7] hreq 329 317 318 328 326 327 note : the ivr is only read by an mc680xx host processor using non-multiplexed mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-33 ac electrical characteristics figure 2-28. read timing diagram, non-multiplexed bus, single data strobe figure 2-29. read timing diagram, non-multiplexed bus, double data strobe hds ha[2?0] hcs h[7?0] 327 332 319 318 317 330 329 337 336 328 326 338 341 340 333 hreq (single host request) hrw 336 337 hrrq (double host request) hrd ha[2?0] hcs h[7?0] 327 332 319 318 317 330 329 337 336 328 326 338 341 340 333 hreq (single host request) hrrq (double host request) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-34 ac electrical characteristics figure 2-30. write timing diagram, non-multiplexed bus, single data strobe figure 2-31. write timing diagram, non-multiplexed bus, double data strobe hds ha[2?0] hcs h[7?0] 324 321 320 331 337 336 339 341 340 333 hreq (single host request) hrw 336 337 htrq (double host request) 325 hwr ha[2?0] hcs h[7?0] 324 321 320 331 325 337 336 339 341 340 333 hreq (single host request) htrq (double host request) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-35 ac electrical characteristics , figure 2-32. read timing diagram, multiplexed bus, single data strobe figure 2-33. read timing diagram, multiplexed bus, double data strobe hds ha[10?8] has had[7?0] hreq (single host request) address data 317 318 319 328 329 327 326 335 336 337 334 341 340 338 323 322 hrrq (double host request) hrw 336 337 hrd ha[10?8] has had[7?0] address data 317 318 319 328 329 327 326 335 336 337 334 341 340 338 323 322 hreq (single host request) hrrq (double host request) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-36 ac electrical characteristics , figure 2-34. write timing diagram, multiplexed bus, single data strobe figure 2-35. write timing diagram, multiplexed bus, double data strobe hds ha[10?8] hreq (single host request) has had[7?0] address data 320 321 325 324 335 341 339 336 334 340 322 323 hrw 336 337 htrq (double host request) 337 hwr ha[10?8] has had[7?0] address data 320 321 325 324 335 341 339 336 334 340 322 323 hreq (single host request) htrq (double host request) 337 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-37 ac electrical characteristics 2.6.7 sci timing table 2-17. sci timings no. characteristics 1 symbol expression 100 mhz unit min max 400 synchronous clock cycle t scc 2 8 t c 53.3 ? ns 401 clock low period t scc /2 ? 10.0 16.7 ? ns 402 clock high period t scc /2 ? 10.0 16.7 ? ns 403 output data setup to clock falling edge (internal clock) t scc /4 + 0.5 t c ? 17.0 8.0 ? ns 404 output data hold after clock rising edge (internal clock) t scc /4 ? 0.5 t c 15.0 ? ns 405 input data setup time before clock rising edge (internal clock) t scc /4 + 0.5 t c + 25.0 50.0 ? ns 406 input data not valid before clock rising edge (internal clock) t scc /4 + 0.5 t c ? 5.5 ? 19.5 ns 407 clock falling edge to output data valid (external clock) ?32.0ns 408 output data hold after clock rising edge (external clock) t c + 8.0 18.0 ? ns 409 input data setup time before clock rising edge (external clock) 0.0 ? ns 410 input data hold time after clock rising edge (external clock) 9.0 ? ns 411 asynchronous clock cycle t acc 3 64 t c 640.0 ? ns 412 clock low period t acc /2 ? 10.0 310.0 ? ns 413 clock high period t acc /2 ? 10.0 310.0 ? ns 414 output data setup to clock rising edge (internal clock) t acc /2 ? 30.0 290.0 ? ns 415 output data hold after clock rising edge (internal clock) t acc /2 ? 30.0 290.0 ? ns notes: 1. v cc = 3.3 v 0.3 v; t j = ? 40c to +100 c, c l = 50 pf. 2. t scc = synchronous clock cycle time (for internal clock, t scc is determined by the sci clock control register and t c ). 3. t acc = asynchronous clock cycle time; value given for 1x clock mode (for internal clock, t acc is determined by the sci clock control register and t c ). 4. an expression is used to compute the number listed as the minimum or maximum value as appropriate. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-38 ac electrical characteristics figure 2-36. sci synchronous mode timing figure 2-37. sci asynchronous mode timing a) internal clock data valid data valid b) external clock data valid sclk (output) txd rxd sclk (input) txd rxd data valid 400 402 404 401 403 405 406 400 402 401 407 409 410 408 1x sclk (output) txd data valid 413 411 412 414 415 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-39 ac electrical characteristics 2.6.8 essi0/essi1 timing table 2-18. essi timings no. characteristics 4, 5, 7 symbol expression 9 100 mhz cond- ition 5 unit min max 430 clock cycle 1 t ssicc 3 t c 4 t c 30.0 40.0 ? ? x ck i ck ns 431 clock high period for internal clock for external clock 2 t c - 10.0 1.5 t c 10.0 15.0 ? ? ns ns 432 clock low period for internal clock for external clock 2 t c ? 10.0 1.5 t c 10.0 15.0 ? ? ns ns 433 rxc rising edge to fsr out (bit-length) high ? ? 37.0 22.0 x ck i ck a ns 434 rxc rising edge to fsr out (bit-length) low ? ? 37.0 22.0 x ck i ck a ns 435 rxc rising edge to fsr out (word-length-relative) high 2 ? ? 39.0 37.0 x ck i ck a ns 436 rxc rising edge to fsr out (word-length-relative) low 2 ? ? 39.0 37.0 x ck i ck a ns 437 rxc rising edge to fsr out (word-length) high ? ? 36.0 21.0 x ck i ck a ns 438 rxc rising edge to fsr out (word-length) low ? ? 37.0 22.0 x ck i ck a ns 439 data in setup time before rxc (sck in synchronous mode) falling edge 10.0 19.0 ? ? x ck i ck ns 440 data in hold time after rxc falling edge 5.0 3.0 ? ? x ck i ck ns 441 fsr input (bl, wr) high before rxc falling edge 2 1.0 23.0 ? ? x ck i ck a ns 442 fsr input (wl) high before rxc falling edge 3.5 23.0 ? ? x ck i ck a ns 443 fsr input hold time after rxc falling edge 3.0 0.0 ? ? x ck i ck a ns 444 flags input setup before rxc falling edge 5.5 19.0 ? ? x ck i ck s ns 445 flags input hold time after rxc falling edge 6.0 0.0 ? ? x ck i ck s ns 446 txc rising edge to fst out (bit-length) high ? ? 29.0 15.0 x ck i ck ns 447 txc rising edge to fst out (bit-length) low ? ? 31.0 17.0 x ck i ck ns 448 txc rising edge to fst out (word-length-relative) high 2 ? ? 31.0 17.0 x ck i ck ns 449 txc rising edge to fst out (word-length-relative) low 2 ? ? 33.0 19.0 x ck i ck ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-40 ac electrical characteristics 450 txc rising edge to fst out (word-length) high ? ? 30.0 16.0 x ck i ck ns 451 txc rising edge to fst out (word-length) low ? ? 31.0 17.0 x ck i ck ns 452 txc rising edge to data out enable from high impedance ? ? 31.0 17.0 x ck i ck ns 453 txc rising edge to transmitter #0 drive enable assertion ? ? 34.0 20.0 x ck i ck ns 454 txc rising edge to data out valid ? ? 20.0 8 10.0 x ck i ck ns 455 txc rising edge to data out high impedance 3 ? ? 31.0 16.0 x ck i ck ns 456 txc rising edge to transmitter #0 drive enable deassertion 3 ? ? 34.0 20.0 x ck i ck ns 457 fst input (bl, wr) setup time before txc falling edge 2 2.0 21.0 ? ? x ck i ck ns 458 fst input (wl) to data out enable from high impedance ? 27.0 ? ns 459 fst input (wl) to transmitter #0 drive enable assertion ? 31.0 ? ns 460 fst input (wl) setup time before txc falling edge 2.5 21.0 ? ? x ck i ck ns 461 fst input hold time after txc falling edge 4.0 0.0 ? ? x ck i ck ns 462 flag output valid after txc rising edge ? ? 32.0 18.0 x ck i ck ns notes: 1. for the internal clock, the external clock cycle is defined by icyc (see timing 7) and the essi control register. 2. the word-length-relative frame sync signal waveform operates the same way as the bit-length frame sync signal waveform, but spreads from one serial clock before the first bit clock (same as the bit length frame sync signal) until the one before last bit clock of the first word in the frame. 3. periodically sampled and not 100 percent tested 4. v cc = 3.3 v 0.3 v; t j = ? 40c to +100 c, c l = 50 pf 5. txc (sck pin) = transmit clock rxc (sc0 or sck pin) = receive clock fst (sc2 pin) = transmit frame sync fsr (sc1 or sc2 pin) receive frame sync 6. i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that txc and rxc are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that txc and rxc are the same clock) 7. bl = bit length; wl = word length; wr = word length relative 8. if the dsp core writes to the transmit register during the last cycle before causing an underrun error, the delay is 20 ns + (0.5 t c ). 9. an expression is used to compute the number listed as the minimum or maximum value as appropriate. table 2-18. essi timings (continued) no. characteristics 4, 5, 7 symbol expression 9 100 mhz cond- ition 5 unit min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-41 ac electrical characteristics figure 2-38. essi transmitter timing last see note note: in network mode, output flag transitions can occur at the start of each time slot within the frame. in normal mode, the output flag state is asserted for the entire frame period. first 430 432 446 447 450 451 455 454 454 452 459 456 453 461 457 458 460 461 462 431 txc (input/ output) fst (bit) out fst (word) out data out transmitter #0 drive enable fst (bit) in fst (word) in flags out f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-42 ac electrical characteristics figure 2-39. essi receiver timing last bit first bit 430 432 433 437 438 440 439 443 441 442 443 445 444 431 434 rxc (input/ output) fsr (bit) out fsr (word) out data in fsr (bit) in fsr (word) in flags in f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-43 ac electrical characteristics 2.6.9 timer timing table 2-19. timer timing 1 no. characteristics expression 2 100 mhz unit min max 480 tio low 2 t c + 2.0 22.0 ? ns 481 tio high 2 t c + 2.0 22.0 ? ns 482 timer set-up time from tio (input) assertion to clkout rising edge 9.0 10.0 ns 483 synchronous timer delay time from clkout rising edge to the external memory access address out valid caused by first interrupt instruction execution 10.25 t c + 1.0 103.5 ? ns 484 clkout rising edge to tio (output) assertion minimum maximum 0.5 t c + 0.5 0.5 t c + 19.8 5.5 ? ? 24.8 ns ns 485 clkout rising edge to tio (output) deassertion minimum maximum 0.5 t c + 0.5 0.5 t c + 19.8 5.5 ? ? 24.8 ns ns notes: 1. v cc = 3.3 v 0.3 v; t j = ? 40c to +100 c, c l = 50 pf 2. an expression is used to compute the number listed as the minimum or maximum value as appropriate. figure 2-40. tio timer event input restrictions figure 2-41. timer interrupt generation figure 2-42. external pulse generation tio 481 480 clkout tio (input) first interrupt instruction execution address 482 483 clkout tio (output) 484 485 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-44 ac electrical characteristics 2.6.10 gpio timing table 2-20. gpio timing no. characteristics expression 100 mhz unit min max 490 clkout edge to gpio out valid (gpio out delay time) ?8.5ns 491 clkout edge to gpio out not valid (gpio out hold time) 0.0 ? ns 492 gpio in valid to clkout edge (gpio in set-up time) 8.5 ? ns 493 clkout edge to gpio in not valid (gpio in hold time) 0.0 ? ns 494 fetch to clkout edge before gpio change minimum: 6.75 t c 67.5 ? ns note: v cc = 3.3 v 0.3 v; t j = ? 40c to +100 c, c l = 50 pf figure 2-43. gpio timing valid gpio (input) gpio (output) clkout (output) fetch the instruction move x0,x:(r0); x0 contains the new value of gpio and r0 contains the address of the gpio data register. a[0?17] 490 491 492 494 493 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-45 ac electrical characteristics 2.6.11 jtag timing table 2-21. jtag timing no. characteristics all frequencies unit min max 500 tck frequency of operation (1/(t c 3); maximum 22 mhz) 0.0 22.0 mhz 501 tck cycle time in crystal mode 45.0 ? ns 502 tck clock pulse width measured at 1.5 v 20.0 ? ns 503 tck rise and fall times 0.0 3.0 ns 504 boundary scan input data setup time 5.0 ? ns 505 boundary scan input data hold time 24.0 ? ns 506 tck low to output data valid 0.0 40.0 ns 507 tck low to output high impedance 0.0 40.0 ns 508 tms, tdi data setup time 5.0 ? ns 509 tms, tdi data hold time 25.0 ? ns 510 tck low to tdo data valid 0.0 44.0 ns 511 tck low to tdo high impedance 0.0 44.0 ns 512 trst assert time 100.0 ? ns 513 trst setup time to tck low 40.0 ? ns notes: 1. v cc = 3.3 v 0.3 v; t j = ?40c to +100 c, c l = 50 pf 2. all timings apply to once module data transfers because it uses the jtag port as an interface. figure 2-44. test clock input timing diagram tck (input) v m v ih v il 501 502 502 503 503 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-46 ac electrical characteristics figure 2-45. boundary scan (jtag) timing diagram figure 2-46. test access port timing diagram figure 2-47. trst timing diagram tck (input) data inputs data outputs data outputs data outputs v ih v il input data valid output data valid output data valid 505 504 506 507 506 tck (input) tdi (input) tdo (output) tdo (output) tdo (output) v ih v il input data valid output data valid output data valid tms 508 509 510 511 510 tck (input) trst (input) 513 512 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-47 ac electrical characteristics 2.6.12 once module timing table 2-22. once module timing no. characteristics expression min max unit 500 tck frequency of operation max 22.0 mhz 0.0 22.0 mhz 514 de assertion time in order to enter debug mode 1.5 t c + 10.0 20.0 ? ns 515 response time when DSP56303 is executing nop instructions from internal memory 5.5 t c + 30.0 ? 67.0 ns 516 debug acknowledge assertion time 3 t c + 5.0 25.0 ? ns note: v cc = 3.3 v 0.3 v, v cc = 1.8 v 0.1 v; t j = ?40c to +100 c, c l = 50 pf figure 2-48. once?debug request de 516 515 514 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-48 ac electrical characteristics f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-1 chapter 3 packaging 3.1 pin-out and package information this section includes diagrams of the DSP56303 package pin-outs and tables showing how the signals described in chapter 1 are allocated for each package. the DSP56303 is available in two package types: 144-pin thin quad flat pack (tqfp) 196-pin molded array process-ball grid array (map-bga) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-2 tqfp package description 3.2 tqfp package description top and bottom views of the tqfp package are shown in figure 3-1 and figure 3-2 with their pin-outs. figure 3-1. DSP56303 thin quad flat pack (tqfp), top view srd1 std1 sc02 sc01 de pinit srd0 v ccs gnd s std0 sc10 sc00 rxd txd sclk sck1 sck0 v ccq gnd q nc hds hrw hack hreq v ccs gnd s tio2 tio1 tio0 hcs ha9 ha8 has had7 had6 had5 had4 v cch gnd h had3 had2 had1 had0 reset v ccp pcap gnd p gnd p1 nc aa3 aa2 cas xtal gnd q extal v ccq v ccc gnd c clkout bclk bclk ta br bb v ccc gnd c wr rd aa1 aa0 bg a0 d7 d8 v ccd gnd d d9 d10 d11 d12 d13 d14 v ccd gnd d d15 d16 d17 d18 d19 v ccq gnd q d20 v ccd gnd d d21 d22 d23 trst tdo tdi tck tms sc12 sc11 1 37 73 109 (top view) orientation mark a1 v cca gnd a a2 a3 a4 a5 v cca gnd a a6 a7 a8 a9 v cca gnd a a10 a11 gnd q v cc q a12 a13 a14 v cca gnd a a15 a16 a17 d0 d1 d2 v ccd gnd d d3 d4 d5 d6 modd modc modb moda notes: because of size constraints in this figure, only one name is shown for multiplexed pins. refer to table 3-1 and table 3-2 for detailed information about pin functions and signal names. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-3 tqfp package description figure 3-2. DSP56303 thin quad flat pack (tqfp), bottom view srd1 std1 sc02 sc01 de pinit srd0 v ccs gnd s std0 sc10 sc00 rxd txd sclk sck1 sck0 v ccq gnd q nc hds hrw hack hreq v ccs gnd s tio2 tio1 tio0 hcs ha9 ha8 has had7 had6 had5 had4 v cc h gnd h had3 had2 had1 had0 reset v ccp pcap gnd p gnd p1 nc aa3 aa2 cas xtal gnd q extal v cc q v ccc gnd c clkout bclk bclk ta br bb v ccc gnd c wr rd aa1 aa0 bg a0 d7 d8 v ccd gnd d d9 d10 d11 d12 d13 d14 v ccd gnd d d15 d16 d17 d18 d19 v ccq gnd q d20 v ccd gnd d d21 d22 d23 modd modc modb moda trst tdo tdi tck tms sc12 sc11 1 37 73 109 (bottom view) a1 v cca gnd a a2 a3 a4 a5 v cca gnd a a6 a7 a8 a9 v cca gnd a a10 a11 gnd q v cc q a12 a13 a14 v cca gnd a a15 a16 a17 d0 d1 d2 v ccd gnd d d3 d4 d5 d6 orientation mark (on top side) notes: because of size constraints in this figure, only one name is shown for multiplexed pins. refer to table 3-1 and table 3-2 for detailed information about pin functions and signal names. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-4 tqfp package description table 3-1. DSP56303 tqfp signal identification by pin number pin no. signal name pin no. signal name pin no. signal name 1 srd1 or pd4 26 gnd s 51 aa2/ras2 2 std1 or pd5 27 tio2 52 cas 3 sc02 or pc2 28 tio1 53 xtal 4 sc01 or pc1 29 tio0 54 gnd q 5de 30 hcs /hcs, ha10, or pb13 55 extal 6 pinit/nmi 31 ha2, ha9, or pb10 56 v ccq 7 srd0 or pc4 32 ha1, ha8, or pb9 57 v ccc 8v ccs 33 ha0, has /has, or pb8 58 gnd c 9gnd s 34 h7, had7, or pb7 59 clkout 10 std0 or pc5 35 h6, had6, or pb6 60 bclk 11 sc10 or pd0 36 h5, had5, or pb5 61 bclk 12 sc00 or pc0 37 h4, had4, or pb4 62 ta 13 rxd or pe0 38 v cch 63 br 14 txd or pe1 39 gnd h 64 bb 15 sclk or pe2 40 h3, had3, or pb3 65 v ccc 16 sck1 or pd3 41 h2, had2, or pb2 66 gnd c 17 sck0 or pc3 42 h1, had1, or pb1 67 wr 18 v ccq 43 h0, had0, or pb0 68 rd 19 gnd q 44 reset 69 aa1/ras1 20 not connected (nc), reserved 45 v ccp 70 aa0/ras0 21 hds /hds, hwr /hwr, or pb12 46 pcap 71 bg 22 hrw, hrd /hrd, or pb11 47 gnd p 72 a0 23 hack /hack, hrrq /hrrq, or pb15 48 gnd p1 73 a1 24 hreq /hreq, htrq /htrq, or pb14 49 not connected (nc), reserved 74 v cca 25 v ccs 50 aa3/ras3 75 gnd a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-5 tqfp package description 76 a2 99 a17 122 d16 77 a3 100 d0 123 d17 78 a4 101 d1 124 d18 79 a5 102 d2 125 d19 80 v cca 103 v ccd 126 v ccq 81 gnd a 104 gnd d 127 gnd q 82 a6 105 d3 128 d20 83 a7 106 d4 129 v ccd 84 a8 107 d5 130 gnd d 85 a9 108 d6 131 d21 86 v cca 109 d7 132 d22 87 gnd a 110 d8 133 d23 88 a10 111 v ccd 134 modd/irqd 89 a11 112 gnd d 135 modc/irqc 90 gnd q 113 d9 136 modb/irqb 91 v ccq 114 d10 137 moda/irqa 92 a12 115 d11 138 trst 93 a13 116 d12 139 tdo 94 a14 117 d13 140 tdi 95 v cca 118 d14 141 tck 96 gnd a 119 v ccd 142 tms 97 a15 120 gnd d 143 sc12 or pd2 98 a16 121 d15 144 sc11 or pd1 notes: signal names are based on configured functionality. most pins supply a single signal. some pins provide a signal with dual functionality, such as the modx/irqx pins that select an operating mode after reset is deasserted but act as interrupt lines during operation. some signals have configurable polarity; these names are shown with and without overbars, such as has /has. some pins have two or more configurable functions; names assigned to these pins indicate the function for a specific configuration. for example, pin 34 is data line h7 in non-multiplexed bus mode, data/address line had7 in multiplexed bus mode, or gpio line pb7 when the gpio function is enabled for this pin. table 3-1. DSP56303 tqfp signal identification by pin number (continued) pin no. signal name pin no. signal name pin no. signal name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-6 tqfp package description table 3-2. DSP56303 tqfp signal identification by name signal name pin no. signal name pin no. signal name pin no. a0 72 bg 71 d7 109 a1 73 br 63 d8 110 a10 88 cas 52 d9 113 a11 89 clkout 59 de 5 a12 92 d0 100 extal 55 a13 93 d1 101 gnd a 75 a1494d10114gnd a 81 a1597d11115gnd a 87 a1698d12116gnd a 96 a1799d13117gnd c 58 a2 76 d14 118 gnd c 66 a3 77 d15 121 gnd d 104 a4 78 d16 122 gnd d 112 a5 79 d17 123 gnd d 120 a6 82 d18 124 gnd d 130 a7 83 d19 125 gnd h 39 a8 84 d2 102 gnd p 47 a9 85 d20 128 gnd p1 48 aa0 70 d21 131 gnd q 19 aa1 69 d22 132 gnd q 54 aa2 51 d23 133 gnd q 90 aa3 50 d3 105 gnd q 127 bb 64 d4 106 gnd s 9 bclk 60 d5 107 gnd s 26 bclk 61 d6 108 h0 43 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-7 tqfp package description h1 42 hrd /hrd 22 pb2 41 h2 41 hreq /hreq 24 pb3 40 h3 40 hrrq /hrrq 23 pb4 37 h4 37 hrw 22 pb5 36 h5 36 htrq /htrq 24 pb6 35 h6 35 hwr /hwr 21 pb7 34 h7 34 irqa 137 pb8 33 ha0 33 irqb 136 pb9 32 ha1 32 irqc 135 pc0 12 ha10 30 irqd 134 pc1 4 ha2 31 moda 137 pc2 3 ha8 32 modb 136 pc3 17 ha9 31 modc 135 pc4 7 hack /hack 23 modd 134 pc5 10 had0 43 nc 20 pcap 46 had1 42 nmi 6 pd0 11 had2 41 nc 49 pd1 144 had3 40 pb0 43 pd2 143 had4 37 pb1 42 pd3 16 had5 36 pb10 31 pd4 1 had6 35 pb11 22 pd5 2 had7 34 pb12 21 pe0 13 has /has 33 pb13 30 pe1 14 hcs /hcs 30 pb14 24 pe2 15 hds /hds 21 pb15 23 pinit 6 table 3-2. DSP56303 tqfp signal identification by name (continued) signal name pin no. signal name pin no. signal name pin no. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-8 tqfp package description ras0 70 srd1 1 v ccc 57 ras1 69 std0 10 v ccc 65 ras2 51 std1 2 v ccd 103 ras3 50 ta 62 v ccd 111 rd 68 tck 141 v ccd 119 reset 44 tdi 140 v ccd 129 rxd 13 tdo 139 v cch 38 sc00 12 tio0 29 v ccp 45 sc01 4 tio1 28 v ccq 18 sc02 3 tio2 27 v ccq 56 sc10 11 tms 142 v ccq 91 sc11 144 trst 138 v ccq 126 sc12 143 txd 14 v ccs 8 sck0 17 v cca 74 v ccs 25 sck1 16 v cca 80 wr 67 sclk 15 v cca 86 xtal 53 srd0 7 v cca 95 table 3-2. DSP56303 tqfp signal identification by name (continued) signal name pin no. signal name pin no. signal name pin no. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-9 tqfp package mechanical drawing 3.3 tqfp package mechanical drawing figure 3-3. DSP56303 mechanical information, 144-pin tqfp package seating plane 0.1 t 144x c 2 view ab 2 t plating f aa j d base metal section j1-j1 (rotated 90) 144 pl m 0.08 n tl-m n 0.20 t l-m 144 73 109 37 108 1 36 72 4x 4x 36 tips pin 1 ident view y b b1 v1 a1 s1 v a s n 0.20 t l-m m l n p 4x g 140x j1 j1 view y c l x x=l, m or n gage plane 0.05 (z) r2 e c2 (y) r1 (k) c1 1 0.25 view ab dim min max millimeters a 20.00 bsc a1 10.00 bsc b 20.00 bsc b1 10.00 bsc c 1.40 1.60 c1 0.05 0.15 c2 1.35 1.45 d 0.17 0.27 e 0.45 0.75 f 0.17 0.23 g 0.50 bsc j 0.09 0.20 k 0.50 ref p 0.25 bsc r1 0.13 0.20 r2 0.13 0.20 s 22.00 bsc s1 11.00 bsc v 22.00 bsc v1 11.00 bsc y 0.25 ref z 1.00 ref aa 0.09 0.16 0 0 7 11 13 1 2 notes: 1. dimensions and tolerancing per asme y14.5, 1994. 2. dimensions in millimeters. 3. datums l, m and n to be determined at the seating plane, datum t. 4. dimensions s and v to be determined at the seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane h. 6. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.35. case 918-03 ? issue c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-10 map-bga package description 3.4 map-bga package description top and bottom views of the map-bga package are shown in figure 3-4 and figure 3-5 with their pin-outs. figure 3-4. DSP56303 molded array process-ball grid array (map-bga), top view 134 2567810 14 13 12 11 9 nc hack hreq b c d e f g h n m l j k ha0 hrw hds hcs modd h5 nc h7 ha1 ha2 h2 v ccd v ccq moda d19 d18 v ccd v ccd v ccq v ccs v cca gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v cca v ccc v cca v cca v ccp v cch v ccs v ccq gnd gnd gnd gnd gnd gnd v ccd nc modc h4 h6 v ccq d12 d11 d15 d9 d5 d3 d0 a0 a17 a16 a1 a2 h1 pb0 h3 tio1 rxd tio2 tio0 sck1 txd sc12 sc11 std1 sck0 srd0 srd1 std0 sc02 sc01 tdo tms de ta tdi tck a15 a12 a7 a5 bg gnd p pinit aa0 trst sclk v ccc p a modb d23 d22 d21 d20 d17 d16 d14 d13 d10 d8 d7 d6 d4 d2 d1 a14 a13 a11 a10 a9 a8 a6 a4 a3 aa1 rd wr bb br bclk bclk clk out xtal cas aa3 aa2 gnd p1 pcap reset sc00 sc10 nc nc nc nc gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd extal top view f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-11 map-bga package description figure 3-5. DSP56303 molded array process-ball grid array (map-bga), bottom view bottom view 1 3 42 5 6 7 8 10 14 13 12 11 9 nc hack hreq b c d e f g h n m l j k ha0 hrw hds hcs modd h5 nc h7 ha1 ha2 h2 v ccd v ccq moda d19 d18 v ccd v ccd v ccq v ccs v cca gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v cca v ccc v cca v cca v ccp v cch v ccs v ccq gnd gnd gnd gnd gnd gnd v ccd nc modc h4 h6 v ccq d12 d11 d15 d9 d5 d3 d0 a0 a17 a16 a1 a2 h1 pb0 h3 tio1 rxd tio2 tio0 sck1 txd sc12 sc11 std1 sck0 srd0 srd1 std0 sc02 sc01 tdo tms de ta tdi tck a15 a12 a7 a5 bg gnd p pinit aa0 trst sclk v ccc p a modb d23 d22 d21 d20 d17 d16 d14 d13 d10 d8 d7 d6 d4 d2 d1 a14 a13 a11 a10 a9 a8 a6 a4 a3 aa1 rd wr bb br bclk bclk clk out xtal cas aa3 aa2 gnd p1 pcap reset sc00 sc10 nc nc nc nc gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd extal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-12 map-bga package description table 3-3. DSP56303 map-bga signal identification by pin number pin no. signal name pin no. signal name pin no. signal name a1 not connected (nc), reserved b12 d8 d9 gnd a2 sc11 or pd1 b13 d5 d10 gnd a3 tms b14 nc d11 gnd a4 tdo c1 sc02 or pc2 d12 d1 a5 modb/irqb c2 std1 or pd5 d13 d2 a6 d23 c3 tck d14 v ccd a7 v ccd c4 moda/irqa e1 std0 or pc5 a8 d19 c5 modc/irqc e2 v ccs a9d16c6d22e3srd0 or pc4 a10 d14 c7 v ccq e4 gnd a11 d11 c8 d18 e5 gnd a12 d9 c9 v ccd e6 gnd a13 d7 c10 d12 e7 gnd a14 nc c11 v ccd e8 gnd b1 srd1 or pd4 c12 d6 e9 gnd b2 sc12 or pd2 c13 d3 e10 gnd b3 tdi c14 d4 e11 gnd b4 trst d1 pinit/nmi e12 a17 b5 modd/irqd d2 sc01 or pc1 e13 a16 b6 d21 d3 de e14 d0 b7 d20 d4 gnd f1 rxd or pe0 b8 d17 d5 gnd f2 sc10 or pd0 b9 d15 d6 gnd f3 sc00 or pc0 b10 d13 d7 gnd f4 gnd b11 d10 d8 gnd f5 gnd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-13 map-bga package description f6 gnd h3 sck0 or pc3 j14 a9 f7 gnd h4 gnd k1 v ccs f8 gnd h5 gnd k2 hreq /hreq, htrq /htrq, or pb14 f9 gnd h6 gnd k3 tio2 f10 gnd h7 gnd k4 gnd f11 gnd h8 gnd k5 gnd f12 v cca h9 gnd k6 gnd f13 a14 h10 gnd k7 gnd f14 a15 h11 gnd k8 gnd g1 sck1 or pd3 h12 v cca k9 gnd g2 sclk or pe2 h13 a10 k10 gnd g3 txd or pe1 h14 a11 k11 gnd g4 gnd j1 hack /hack, hrrq /hrrq, or pb15 k12 v cca g5 gnd j2 hrw, hrd /hrd, or pb11 k13 a5 g6 gnd j3 hds /hds, hwr /hwr, or pb12 k14 a6 g7 gnd j4 gnd l1 hcs /hcs, ha10, or pb13 g8 gnd j5 gnd l2 tio1 g9 gnd j6 gnd l3 tio0 g10 gnd j7 gnd l4 gnd g11 gnd j8 gnd l5 gnd g12 a13 j9 gnd l6 gnd g13 v ccq j10 gnd l7 gnd g14 a12 j11 gnd l8 gnd h1 nc j12 a8 l9 gnd h2 v ccq j13a7l10gnd l11 gnd m13 a1 p1 nc l12 v cca m14 a2 p2 h5, had5, or pb5 l13 a3 n1 h6, had6, or pb6 p3 h3, had3, or pb3 table 3-3. DSP56303 map-bga signal identification by pin number (continued) pin no. signal name pin no. signal name pin no. signal name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-14 map-bga package description l14 a4 n2 h7, had7, or pb7 p4 h1, had1, or pb1 m1 ha1, ha8, or pb9 n3 h4, had4, or pb4 p5 pcap m2 ha2, ha9, or pb10 n4 h2, had2, or pb2 p6 gnd p1 m3 ha0, has /has, or pb8 n5 reset p7 aa2/ras2 m4 v cch n6 gnd p p8 xtal m5 h0, had0, or pb0 n7 aa3/ras3 p9 v ccc m6 v ccp n8 cas p10 ta m7 nc n9 v ccq p11 bb m8 extal n10 bclk p12 aa1/ras1 m9 clkout n11 br p13 bg m10 bclk n12 v ccc p14 nc m11 wr n13 aa0/ras0 m12 rd n14 a0 notes: signal names are based on configured functionality. most connections supply a single signal. some connections provide a signal with dual functionality, such as the modx/irqx pins that select an operating mode after reset is deasserted but act as interrupt lines during operation. some signals have configurable polarity; these names are shown with and without overbars, such as has /has. some connections have two or more configurable functions; names assigned to these connections indicate the function for a specific configuration. for example, connection n2 is data line h7 in non-multiplexed bus mode, data/address line had7 in multiplexed bus mode, or gpio line pb7 when the gpio function is enabled for this pin. unlike in the tqfp package, most of the gnd pins are connected internally in the center of the connection array and act as heat sink for the chip. therefore, except for gnd p and gnd p1 that support the pll, other gnd signals do not support individual subsystems in the chip . table 3-3. DSP56303 map-bga signal identification by pin number (continued) pin no. signal name pin no. signal name pin no. signal name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-15 map-bga package description table 3-4. DSP56303 map-bga signal identification by name signal name pin no. signal name pin no. signal name pin no. a0 n14 bg p13 d7 a13 a1 m13 br n11d8b12 a10 h13 cas n8 d9 a12 a11 h14 clkout m9 de d3 a12 g14 d0 e14 extal m8 a13 g12 d1 d12 gnd d4 a14 f13 d10 b11 gnd d5 a15 f14 d11 a11 gnd d6 a16 e13 d12 c10 gnd d7 a17e12d13b10gndd8 a2 m14 d14 a10 gnd d9 a3 l13 d15 b9 gnd d10 a4 l14 d16 a9 gnd d11 a5 k13 d17 b8 gnd e4 a6 k14 d18 c8 gnd e5 a7 j13 d19 a8 gnd e6 a8 j12 d2 d13 gnd e7 a9 j14 d20 b7 gnd e8 aa0 n13 d21 b6 gnd e9 aa1 p12 d22 c6 gnd e10 aa2 p7 d23 a6 gnd e11 aa3 n7 d3 c13 gnd f4 bb p11d4c14gndf5 bclk m10 d5 b13 gnd f6 bclk n10 d6 c12 gnd f7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-16 map-bga package description gnd f8 gnd j9 h4 n3 gnd f9 gnd j10 h5 p2 gnd f10 gnd j11 h6 n1 gnd f11 gnd k4 h7 n2 gnd g4 gnd k5 ha0 m3 gnd g5 gnd k6 ha1 m1 gnd g6 gnd k7 ha10 l1 gnd g7 gnd k8 ha2 m2 gnd g8 gnd k9 ha8 m1 gnd g9 gnd k10 ha9 m2 gnd g10 gnd k11 hack /hack j1 gnd g11 gnd l4 had0 m5 gnd h4 gnd l5 had1 p4 gnd h5 gnd l6 had2 n4 gnd h6 gnd l7 had3 p3 gnd h7 gnd l8 had4 n3 gnd h8 gnd l9 had5 p2 gnd h9 gnd l10 had6 n1 gnd h10 gnd l11 had7 n2 gnd h11 gnd p n6 has /has m3 gnd j4 gnd p1 p6 hcs /hcs l1 gnd j5 h0 m5 hds /hds j3 gnd j6 h1 p4 hrd /hrd j2 gnd j7 h2 n4 hreq /hreq k2 gnd j8 h3 p3 hrrq /hrrq j1 table 3-4. DSP56303 map-bga signal identification by name (continued) signal name pin no. signal name pin no. signal name pin no. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-17 map-bga package description hrw j2 pb14 k2 pe2 g2 htrq /htrq k2 pb15 j1 pinit d1 hwr /hwr j3 pb2 n4 ras0 n13 irqa c4 pb3 p3 ras1 p12 irqb a5 pb4 n3 ras2 p7 irqc c5 pb5 p2 ras3 n7 irqd b5 pb6 n1 rd m12 moda c4 pb7 n2 reset n5 modb a5 pb8 m3 rxd f1 modc c5 pb9 m1 sc00 f3 modd b5 pc0 f3 sc01 d2 nc a1 pc1 d2 sc02 c1 nc a14 pc2 c1 sc10 f2 nc b14 pc3 h3 sc11 a2 nc h1 pc4 e3 sc12 b2 nc m7 pc5 e1 sck0 h3 nc p1 pcap p5 sck1 g1 nc p14 pd0 f2 sclk g2 nmi d1 pd1 a2 srd0 e3 pb0 m5 pd2 b2 srd1 b1 pb1 p4 pd3 g1 std0 e1 pb10 m2 pd4 b1 std1 c2 pb11 j2 pd5 c2 ta p10 pb12 j3 pe0 f1 tck c3 pb13 l1 pe1 g3 tdi b3 table 3-4. DSP56303 map-bga signal identification by name (continued) signal name pin no. signal name pin no. signal name pin no. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-18 map-bga package description tdo a4 v cca k12 v ccp m6 tio0 l3 v cca l12 v ccq c7 tio1 l2 v ccc n12 v ccq g13 tio2 k3 v ccc p9 v ccq h2 tms a3 v ccd a7 v ccq n9 trst b4 v ccd c9 v ccs e2 txd g3 v ccd c11 v ccs k1 v cca f12 v ccd d14 wr m11 v cca h12 v cch m4 xtal p8 table 3-4. DSP56303 map-bga signal identification by name (continued) signal name pin no. signal name pin no. signal name pin no. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-19 map-bga package mechanical drawing 3.5 map-bga package mechanical drawing figure 3-6. DSP56303 mechanical information, 196-pin map-bga package f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-20 map-bga package mechanical drawing f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-1 chapter 4 design considerations 4.1 thermal design considerations an estimate of the chip junction temperature, t j , in c can be obtained from this equation: equation 1: where: t a = ambient temperature c r ja = package junction-to-ambient thermal resistance c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance, as in this equation: equation 2: where: r ja = package junction-to-ambient thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w r jc is device-related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (pcb) or otherwise change the thermal dissipation capability of the area surrounding the device on a pcb. this model is most useful for ceramic packages with heat sinks; some 90 percent of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the pcb, analysis of the device thermal performance may need the additional modeling capability of a system-level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperature of the pcb to which the package is mounted. again, if the estimates obtained from r ja do not satisfactorily answer whether the thermal performance is adequate, a system-level model may be appropriate. t j t a p d r ja () + = r ja r jc r ca + = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-2 electrical design considerations a complicating factor is the existence of three common ways to determine the junction-to-case thermal resistance in plastic packages. to minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. to define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to the point at which the leads attach to the case. if the temperature of the package case (t t ) is determined by a thermocouple, thermal resistance is computed from the value obtained by the equation (t j ? t t )/p d . as noted earlier, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. from a practical standpoint, that value is also suitable to determine the junction temperature from a case thermocouple reading in forced convection environments. in natural convection, the use of the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will yield an estimate of a junction temperature slightly higher than actual temperature. hence, the new thermal metric, thermal characterization parameter or jt , has been defined to be (t j ? t t )/p d . this value gives a better estimate of the junction temperature in natural convection when the surface temperature of the package is used. remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. the recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 4.2 electrical design considerations caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either gnd or v cc ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-3 electrical design considerations use the following list of recommendations to ensure correct dsp operation. provide a low-impedance path from the board power supply to each v cc pin on the dsp and from the board ground to each gnd pin. use at least six 0.01?0.1 f bypass capacitors positioned as close as possible to the four sides of the package to connect the v cc power source to gnd . ensure that capacitor leads and associated printed circuit traces that connect to the chip v cc and gnd pins are less than 0.5 inch per capacitor lead. use at least a four-layer pcb with two inner layers for v cc and gnd . because the dsp output signals have fast rise and fall times, pcb trace lengths should be minimal. this recommendation particularly applies to the address and data buses as well as the irqa , irqb , irqc , irqd , ta , and bg pins. maximum pcb trace lengths on the order of 6 inches are recommended. consider all device loads as well as parasitic capacitance due to pcb traces when you calculate capacitance. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the v cc and gnd circuits. all inputs must be terminated (that is, not allowed to float) by cmos levels except for the three pins with internal pull-up resistors ( trst , tms , de ). take special care to minimize noise levels on the v ccp , gnd p , and gnd p1 pins. the following pins must be asserted after power-up: reset and trst . if multiple dsp devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. reset must be asserted when the chip is powered up. a stable extal signal should be supplied before deassertion of reset . at power-up, ensure that the voltage difference between the 5 v tolerant pins and the chip v cc never exceeds 3.5 v. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-4 power consumption considerations 4.3 power consumption considerations power dissipation is a key issue in portable dsp applications. some of the factors affecting current consumption are described in this section. most of the current consumed by cmos devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. current consumption is described by this formula: equation 3: where: c = node/pin capacitance v = voltage swing f = frequency of node/pin toggle equation 4: the maximum internal current (i cci max) value reflects the typical possible switching of the internal buses on best-case operation conditions?not necessarily a real application case. the typical internal current (i ccityp ) value reflects the average switching of the internal buses on typical operating conditions. perform the following steps for applications that require very low current consumption: 1. set the ebd bit when you are not accessing external memory. 2. minimize external memory accesses, and use internal memory accesses. 3. minimize the number of pins that are switching. 4. minimize the capacitive load on the pins. 5. connect the unused inputs to pull-up or pull-down resistors. 6. disable unused peripherals. 7. disable unused pin activity (for example, clkout , xtal ). one way to evaluate power consumption is to use a current-per-mips measurement methodology to minimize specific board effects (that is, to compensate for measured board current not caused by the dsp). a benchmark power consumption test algorithm is listed in appendix a . use the test algorithm, specific test current measurements, and the following equation to derive the current-per-mips value. equation 5: where: i typf2 = current at f2 i typf1 = current at f1 f2 = high frequency (any specified operating frequency) f1 = low frequency (any specified operating frequency lower than f2) note: f1 should be significantly less than f2. for example, f2 could be 66 mhz and f1 could be 33 mhz. the degree of difference between f1 and f2 determines the amount of precision with which the current rating can be determined for an application. example 4-1. current consumption for a port a address pin loaded with 50 pf capacitance, operating at 3.3 v, with a 66 mhz clock, toggling at its maximum possible rate (33 mhz), the current consumption is expressed in equation 4 . icvf = i 50 10 12 ? 3.3 33 10 6 5.48 ma == i mips ? i mhz ? i typf2 i typf1 ? () f2 f1 ? () ? == f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-5 pll performance issues 4.4 pll performance issues the following explanations should be considered as general observations on expected pll behavior. there is no test that replicates these exact numbers. these observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges. 4.4.1 phase skew performance the phase skew of the pll is defined as the time difference between the falling edges of extal and clkout for a given capacitive load on clkout , over the entire process, temperature and voltage ranges. as defined in figure 2-2 , external clock timing , on page 2-5 for input frequencies greater than 15 mhz and the mf 4, this skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. however, for mf < 10 and input frequencies greater than 10 mhz, this skew is between ? 1.4 ns and +3.2 ns. 4.4.2 phase jitter performance the phase jitter of the pll is defined as the variations in the skew between the falling edges of extal and clkout for a given device in specific temperature, voltage, input frequency, mf, and capacitive load on clkout . these variations are a result of the pll locking mechanism. for input frequencies greater than 15 mhz and mf 4, this jitter is less than 0.6 ns; otherwise, this jitter is not guaranteed. however, for mf < 10 and input frequencies greater than 10 mhz, this jitter is less than 2 ns. 4.4.3 frequency jitter performance the frequency jitter of the pll is defined as the variation of the frequency of clkout . for small mf (mf < 10) this jitter is smaller than 0.5 percent. for mid-range mf (10 < mf < 500) this jitter is between 0.5 percent and approximately 2 percent. for large mf (mf > 500), the frequency jitter is 2?3 percent. 4.5 input (extal) jitter requirements the allowed jitter on the frequency of extal is 0.5 percent. if the rate of change of the frequency of extal is slow (that is, it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time), then the allowed jitter can be 2 percent. the phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed values. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-6 input (extal) jitter requirements f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-1 appendix a power consumption benchmark the following benchmark program evaluates DSP56303 power use in a test situation. it enables the pll, disables the external clock, and uses repeated multiply-accumulate (mac) instructions with a set of synthetic dsp application data to emulate intensive sustained dsp operation. ;************************************************************************** ;************************************************************************** ;* * ;* checks typical power consumption * ;* * ;************************************************************************** page 200,55,0,0,0 nolist i_vec equ $000000; interrupt vectors for program debug only start equ $8000; main (external) program starting address int_prog equ $100 ; internal program memory starting address int_xdat equ $0; internal x-data memory starting address int_ydat equ $0; internal y-data memory starting address include "ioequ.asm" include "intequ.asm" list org p:start ; movep #$0243ff,x:m_bcr ;; bcr: area 3 = 2 w.s (sram) ; default: 2w.s (sram) ; movep #$0d0000,x:m_pctl ; xtal disable ; pll enable ; clkout disable ; ; load the program ; move #int_prog,r0 move #prog_start,r1 do #(prog_end-prog_start),pload_loop move p:(r1)+,x0 move x0,p:(r0)+ nop pload_loop ; ; load the x-data ; move #int_xdat,r0 move #xdat_start,r1 do #(xdat_end-xdat_start),xload_loop move p:(r1)+,x0 move x0,x:(r0)+ xload_loop ; ; load the y-data ; move #int_ydat,r0 move #ydat_start,r1 do #(ydat_end-ydat_start),yload_loop move p:(r1)+,x0 move x0,y:(r0)+ yload_loop ; jmp int_prog prog_start move #$0,r0 move #$0,r4 move #$3f,m0 move #$3f,m4 ; clr a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-2 power consumption benchmark clr b move #$0,x0 move #$0,x1 move #$0,y0 move #$0,y1 bset #4,omr ; ebd ; sbr dor #60,_end mac x0,y0,a x:(r0)+,x1 y:(r4)+,y1 mac x1,y1,a x:(r0)+,x0 y:(r4)+,y0 add a,b mac x0,y0,a x:(r0)+,x1 mac x1,y1,a y:(r4)+,y0 move b1,x:$ff _end bra sbr nop nop nop nop prog_end nop nop xdat_start ; org x:0 dc $262eb9 dc $86f2fe dc $e56a5f dc $616cac dc $8ffd75 dc $9210a dc $a06d7b dc $cea798 dc $8dfbf1 dc $a063d6 dc $6c6657 dc $c2a544 dc $a3662d dc $a4e762 dc $84f0f3 dc $e6f1b0 dc $b3829 dc $8bf7ae dc $63a94f dc $ef78dc dc $242de5 dc $a3e0ba dc $ebab6b dc $8726c8 dc $ca361 dc $2f6e86 dc $a57347 dc $4be774 dc $8f349d dc $a1ed12 dc $4bfce3 dc $ea26e0 dc $cd7d99 dc $4ba85e dc $27a43f dc $a8b10c dc $d3a55 dc $25ec6a dc $2a255b dc $a5f1f8 dc $2426d1 dc $ae6536 dc $cbbc37 dc $6235a4 dc $37f0d dc $63bec2 dc $a5e4d3 dc $8ce810 dc $3ff09 dc $60e50e dc $cffb2f dc $40753c dc $8262c5 dc $ca641a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-3 power consumption benchmark dc $eb3b4b dc $2da928 dc $ab6641 dc $28a7e6 dc $4e2127 dc $482fd4 dc $7257d dc $e53c72 dc $1a8c3 dc $e27540 xdat_end ydat_start ; org y:0 dc $5b6da dc $c3f70b dc $6a39e8 dc $81e801 dc $c666a6 dc $46f8e7 dc $aaec94 dc $24233d dc $802732 dc $2e3c83 dc $a43e00 dc $c2b639 dc $85a47e dc $abfddf dc $f3a2c dc $2d7cf5 dc $e16a8a dc $ecb8fb dc $4bed18 dc $43f371 dc $83a556 dc $e1e9d7 dc $aca2c4 dc $8135ad dc $2ce0e2 dc $8f2c73 dc $432730 dc $a87fa9 dc $4a292e dc $a63ccf dc $6ba65c dc $e06d65 dc $1aa3a dc $a1b6eb dc $48ac48 dc $ef7ae1 dc $6e3006 dc $62f6c7 dc $6064f4 dc $87e41d dc $cb2692 dc $2c3863 dc $c6bc60 dc $43a519 dc $6139de dc $adf7bf dc $4b3e8c dc $6079d5 dc $e0f5ea dc $8230db dc $a3b778 dc $2bfe51 dc $e0a6b6 dc $68ffb7 dc $28f324 dc $8f2e8d dc $667842 dc $83e053 dc $a1fd90 dc $6b2689 dc $85b68e dc $622eaf dc $6162bc dc $e4a245 ydat_end ;************************************************************************** f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-4 power consumption benchmark ; ; equates for DSP56303 i/o registers and ports ; ; last update: june 11 1995 ; ;************************************************************************** page 132,55,0,0,0 opt mex ioequ ident 1,0 ;------------------------------------------------------------------------ ; ; equates for i/o port programming ; ;------------------------------------------------------------------------ ; register addresses m_hdr equ $ffffc9 ; host port gpio data register m_hddr equ $ffffc8 ; host port gpio direction register m_pcrc equ $ffffbf ; port c control register m_prrc equ $ffffbe ; port c direction register m_pdrc equ $ffffbd ; port c gpio data register m_pcrd equ $ffffaf ; port d control register m_prrd equ $ffffae ; port d direction data register m_pdrd equ $ffffad ; port d gpio data register m_pcre equ $ffff9f ; port e control register m_prre equ $ffff9e ; port e direction register m_pdre equ $ffff9d ; port e data register m_ogdb equ $fffffc ; once gdb register ;------------------------------------------------------------------------ ; ; equates for host interface ; ;------------------------------------------------------------------------ ; register addresses m_hcr equ $ffffc2 ; host control register m_hsr equ $ffffc3 ; host status register m_hpcr equ $ffffc4 ; host polarity control register m_hbar equ $ffffc5 ; host base address register m_hrx equ $ffffc6 ; host receive register m_htx equ $ffffc7 ; host transmit register ; hcr bits definition m_hrie equ $0 ; host receive interrupts enable m_htie equ $1 ; host transmit interrupt enable m_hcie equ $2 ; host command interrupt enable m_hf2 equ $3 ; host flag 2 m_hf3 equ $4 ; host flag 3 ; hsr bits definition m_hrdf equ $0 ; host receive data full m_htde equ $1 ; host receive data empty m_hcp equ $2 ; host command pending m_hf0 equ $3 ; host flag 0 m_hf1 equ $4 ; host flag 1 ; hpcr bits definition m_hgen equ $0 ; host port gpio enable m_ha8en equ $1 ; host address 8 enable m_ha9en equ $2 ; host address 9 enable m_hcsen equ $3 ; host chip select enable m_hren equ $4 ; host request enable m_haen equ $5 ; host acknowledge enable m_hen equ $6 ; host enable m_hod equ $8 ; host request open drain mode m_hdsp equ $9 ; host data strobe polarity m_hasp equ $a ; host address strobe polarity m_hmux equ $b ; host multiplexed bus select m_hd_hs equ $c ; host double/single strobe select m_hcsp equ $d ; host chip select polarity m_hrp equ $e ; host request polarity m_hap equ $f ; host acknowledge polarity f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-5 power consumption benchmark ;------------------------------------------------------------------------ ; ; equates for serial communications interface (sci) ; ;------------------------------------------------------------------------ ; register addresses m_stxh equ $ffff97 ; sci transmit data register (high) m_stxm equ $ffff96 ; sci transmit data register (middle) m_stxl equ $ffff95 ; sci transmit data register (low) m_srxh equ $ffff9a ; sci receive data register (high) m_srxm equ $ffff99 ; sci receive data register (middle) m_srxl equ $ffff98 ; sci receive data register (low) m_stxa equ $ffff94 ; sci transmit address register m_scr equ $ffff9c ; sci control register m_ssr equ $ffff93 ; sci status register m_sccr equ $ffff9b ; sci clock control register ; sci control register bit flags m_wds equ $7 ; word select mask (wds0-wds3) m_wds0 equ 0 ; word select 0 m_wds1 equ 1 ; word select 1 m_wds2 equ 2 ; word select 2 m_ssftd equ 3 ; sci shift direction m_sbk equ 4 ; send break m_wake equ 5 ; wakeup mode select m_rwu equ 6 ; receiver wakeup enable m_woms equ 7 ; wired-or mode select m_scre equ 8 ; sci receiver enable m_scte equ 9 ; sci transmitter enable m_ilie equ 10 ; idle line interrupt enable m_scrie equ 11 ; sci receive interrupt enable m_sctie equ 12 ; sci transmit interrupt enable m_tmie equ 13 ; timer interrupt enable m_tir equ 14 ; timer interrupt rate m_sckp equ 15 ; sci clock polarity m_reie equ 16 ; sci error interrupt enable (reie) ; sci status register bit flags m_trne equ 0 ; transmitter empty m_tdre equ 1 ; transmit data register empty m_rdrf equ 2 ; receive data register full m_idle equ 3 ; idle line flag m_or equ 4 ; overrun error flag m_pe equ 5 ; parity error m_fe equ 6 ; framing error flag m_r8 equ 7 ; received bit 8 (r8) address ; sci clock control register m_cd equ $fff ; clock divider mask (cd0-cd11) m_cod equ 12 ; clock out divider m_scp equ 13 ; clock prescaler m_rcm equ 14 ; receive clock mode source bit m_tcm equ 15 ; transmit clock source bit ;------------------------------------------------------------------------ ; ; equates for synchronous serial interface (ssi) ; ;------------------------------------------------------------------------ ; ; register addresses of ssi0 m_tx00 equ $ffffbc ; ssi0 transmit data register 0 m_tx01 equ $ffffbb ; ssio transmit data register 1 m_tx02 equ $ffffba ; ssio transmit data register 2 m_tsr0 equ $ffffb9 ; ssi0 time slot register m_rx0 equ $ffffb8 ; ssi0 receive data register m_ssisr0 equ $ffffb7 ; ssi0 status register m_crb0 equ $ffffb6 ; ssi0 control register b m_cra0 equ $ffffb5 ; ssi0 control register a m_tsma0 equ $ffffb4 ; ssi0 transmit slot mask register a m_tsmb0 equ $ffffb3 ; ssi0 transmit slot mask register b m_rsma0 equ $ffffb2 ; ssi0 receive slot mask register a m_rsmb0 equ $ffffb1 ; ssi0 receive slot mask register b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-6 power consumption benchmark ; register addresses of ssi1 m_tx10 equ $ffffac ; ssi1 transmit data register 0 m_tx11 equ $ffffab ; ssi1 transmit data register 1 m_tx12 equ $ffffaa ; ssi1 transmit data register 2 m_tsr1 equ $ffffa9 ; ssi1 time slot register m_rx1 equ $ffffa8 ; ssi1 receive data register m_ssisr1 equ $ffffa7 ; ssi1 status register m_crb1 equ $ffffa6 ; ssi1 control register b m_cra1 equ $ffffa5 ; ssi1 control register a m_tsma1 equ $ffffa4 ; ssi1 transmit slot mask register a m_tsmb1 equ $ffffa3 ; ssi1 transmit slot mask register b m_rsma1 equ $ffffa2 ; ssi1 receive slot mask register a m_rsmb1 equ $ffffa1 ; ssi1 receive slot mask register b ; ssi control register a bit flags m_pm equ $ff ; prescale modulus select mask (pm0-pm7) m_psr equ 11 ; prescaler range m_dc equ $1f000 ; frame rate divider control mask (dc0-dc7) m_alc equ 18 ; alignment control (alc) m_wl equ $380000 ; word length control mask (wl0-wl7) m_ssc1 equ 22 ; select sc1 as tr #0 drive enable (ssc1) ; ssi control register b bit flags m_of equ $3 ; serial output flag mask m_of0 equ 0 ; serial output flag 0 m_of1 equ 1 ; serial output flag 1 m_scd equ $1c ; serial control direction mask m_scd0 equ 2 ; serial control 0 direction m_scd1 equ 3 ; serial control 1 direction m_scd2 equ 4 ; serial control 2 direction m_sckd equ 5 ; clock source direction m_shfd equ 6 ; shift direction m_fsl equ $180 ; frame sync length mask (fsl0-fsl1) m_fsl0 equ 7 ; frame sync length 0 m_fsl1 equ 8 ; frame sync length 1 m_fsr equ 9 ; frame sync relative timing m_fsp equ 10 ; frame sync polarity m_ckp equ 11 ; clock polarity m_syn equ 12 ; sync/async control m_mod equ 13 ; ssi mode select m_sste equ $1c000 ; ssi transmit enable mask m_sste2 equ 14 ; ssi transmit #2 enable m_sste1 equ 15 ; ssi transmit #1 enable m_sste0 equ 16 ; ssi transmit #0 enable m_ssre equ 17 ; ssi receive enable m_sstie equ 18 ; ssi transmit interrupt enable m_ssrie equ 19 ; ssi receive interrupt enable m_stlie equ 20 ; ssi transmit last slot interrupt enable m_srlie equ 21 ; ssi receive last slot interrupt enable m_steie equ 22 ; ssi transmit error interrupt enable m_sreie equ 23 ; si receive error interrupt enable ; ssi status register bit flags m_if equ $3 ; serial input flag mask m_if0 equ 0 ; serial input flag 0 m_if1 equ 1 ; serial input flag 1 m_tfs equ 2 ; transmit frame sync flag m_rfs equ 3 ; receive frame sync flag m_tue equ 4 ; transmitter underrun error flag m_roe equ 5 ; receiver overrun error flag m_tde equ 6 ; transmit data register empty m_rdf equ 7 ; receive data register full ; ssi transmit slot mask register a m_sstsa equ $ffff ; ssi transmit slot bits mask a (ts0-ts15) ; ssi transmit slot mask register b m_sstsb equ $ffff ; ssi transmit slot bits mask b (ts16-ts31) ; ssi receive slot mask register a m_ssrsa equ $ffff ; ssi receive slot bits mask a (rs0-rs15) ; ssi receive slot mask register b m_ssrsb equ $ffff ; ssi receive slot bits mask b (rs16-rs31) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-7 power consumption benchmark ;------------------------------------------------------------------------ ; ; equates for exception processing ; ;------------------------------------------------------------------------ ; register addresses m_iprc equ $ffffff ; interrupt priority register core m_iprp equ $fffffe ; interrupt priority register peripheral ; interrupt priority register core (iprc) m_ial equ $7 ; irqa mode mask m_ial0 equ 0 ; irqa mode interrupt priority level (low) m_ial1 equ 1 ; irqa mode interrupt priority level (high) m_ial2 equ 2 ; irqa mode trigger mode m_ibl equ $38 ; irqb mode mask m_ibl0 equ 3 ; irqb mode interrupt priority level (low) m_ibl1 equ 4 ; irqb mode interrupt priority level (high) m_ibl2 equ 5 ; irqb mode trigger mode m_icl equ $1c0 ; irqc mode mask m_icl0 equ 6 ; irqc mode interrupt priority level (low) m_icl1 equ 7 ; irqc mode interrupt priority level (high) m_icl2 equ 8 ; irqc mode trigger mode m_idl equ $e00 ; irqd mode mask m_idl0 equ 9 ; irqd mode interrupt priority level (low) m_idl1 equ 10 ; irqd mode interrupt priority level (high) m_idl2 equ 11 ; irqd mode trigger mode m_d0l equ $3000 ; dma0 interrupt priority level mask m_d0l0 equ 12 ; dma0 interrupt priority level (low) m_d0l1 equ 13 ; dma0 interrupt priority level (high) m_d1l equ $c000 ; dma1 interrupt priority level mask m_d1l0 equ 14 ; dma1 interrupt priority level (low) m_d1l1 equ 15 ; dma1 interrupt priority level (high) m_d2l equ $30000 ; dma2 interrupt priority level mask m_d2l0 equ 16 ; dma2 interrupt priority level (low) m_d2l1 equ 17 ; dma2 interrupt priority level (high) m_d3l equ $c0000 ; dma3 interrupt priority level mask m_d3l0 equ 18 ; dma3 interrupt priority level (low) m_d3l1 equ 19 ; dma3 interrupt priority level (high) m_d4l equ $300000 ; dma4 interrupt priority level mask m_d4l0 equ 20 ; dma4 interrupt priority level (low) m_d4l1 equ 21 ; dma4 interrupt priority level (high) m_d5l equ $c00000 ; dma5 interrupt priority level mask m_d5l0 equ 22 ; dma5 interrupt priority level (low) m_d5l1 equ 23 ; dma5 interrupt priority level (high) ; interrupt priority register peripheral (iprp) m_hpl equ $3 ; host interrupt priority level mask m_hpl0 equ 0 ; host interrupt priority level (low) m_hpl1 equ 1 ; host interrupt priority level (high) m_s0l equ $c ; ssi0 interrupt priority level mask m_s0l0 equ 2 ; ssi0 interrupt priority level (low) m_s0l1 equ 3 ; ssi0 interrupt priority level (high) m_s1l equ $30 ; ssi1 interrupt priority level mask m_s1l0 equ 4 ; ssi1 interrupt priority level (low) m_s1l1 equ 5 ; ssi1 interrupt priority level (high) m_scl equ $c0 ; sci interrupt priority level mask m_scl0 equ 6 ; sci interrupt priority level (low) m_scl1 equ 7 ; sci interrupt priority level (high) m_t0l equ $300 ; timer interrupt priority level mask m_t0l0 equ 8 ; timer interrupt priority level (low) m_t0l1 equ 9 ; timer interrupt priority level (high) ;------------------------------------------------------------------------ ; ; equates for timer ; ;------------------------------------------------------------------------ ; register addresses of timer0 m_tcsr0 equ $ffff8f ; timer 0 control/status register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-8 power consumption benchmark m_tlr0 equ $ffff8e ; timer0 load reg m_tcpr0 equ $ffff8d ; timer0 compare register m_tcr0 equ $ffff8c ; timer0 count register ; register addresses of timer1 m_tcsr1 equ $ffff8b ; timer1 control/status register m_tlr1 equ $ffff8a ; timer1 load reg m_tcpr1 equ $ffff89 ; timer1 compare register m_tcr1 equ $ffff88 ; timer1 count register ; register addresses of timer2 m_tcsr2 equ $ffff87 ; timer2 control/status register m_tlr2 equ $ffff86 ; timer2 load reg m_tcpr2 equ $ffff85 ; timer2 compare register m_tcr2 equ $ffff84 ; timer2 count register m_tplr equ $ffff83 ; timer prescaler load register m_tpcr equ $ffff82 ; timer prescalar count register ; timer control/status register bit flags m_te equ 0 ; timer enable m_toie equ 1 ; timer overflow interrupt enable m_tcie equ 2 ; timer compare interrupt enable m_tc equ $f0 ; timer control mask (tc0-tc3) m_inv equ 8 ; inverter bit m_trm equ 9 ; timer restart mode m_dir equ 11 ; direction bit m_di equ 12 ; data input m_do equ 13 ; data output m_pce equ 15 ; prescaled clock enable m_tof equ 20 ; timer overflow flag m_tcf equ 21 ; timer compare flag ; timer prescaler register bit flags m_ps equ $600000 ; prescaler source mask m_ps0 equ 21 m_ps1 equ 22 ; timer control bits m_tc0 equ 4 ; timer control 0 m_tc1 equ 5 ; timer control 1 m_tc2 equ 6 ; timer control 2 m_tc3 equ 7 ; timer control 3 ;------------------------------------------------------------------------ ; ; equates for direct memory access (dma) ; ;------------------------------------------------------------------------ ; register addresses of dma m_dstr equ fffff4 ; dma status register m_dor0 equ $fffff3 ; dma offset register 0 m_dor1 equ $fffff2 ; dma offset register 1 m_dor2 equ $fffff1 ; dma offset register 2 m_dor3 equ $fffff0 ; dma offset register 3 ; register addresses of dma0 m_dsr0 equ $ffffef ; dma0 source address register m_ddr0 equ $ffffee ; dma0 destination address register m_dco0 equ $ffffed ; dma0 counter m_dcr0 equ $ffffec ; dma0 control register ; register addresses of dma1 m_dsr1 equ $ffffeb ; dma1 source address register m_ddr1 equ $ffffea ; dma1 destination address register m_dco1 equ $ffffe9 ; dma1 counter m_dcr1 equ $ffffe8 ; dma1 control register ; register addresses of dma2 m_dsr2 equ $ffffe7 ; dma2 source address register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-9 power consumption benchmark m_ddr2 equ $ffffe6 ; dma2 destination address register m_dco2 equ $ffffe5 ; dma2 counter m_dcr2 equ $ffffe4 ; dma2 control register ; register addresses of dma4 m_dsr3 equ $ffffe3 ; dma3 source address register m_ddr3 equ $ffffe2 ; dma3 destination address register m_dco3 equ $ffffe1 ; dma3 counter m_dcr3 equ $ffffe0 ; dma3 control register ; register addresses of dma4 m_dsr4 equ $ffffdf ; dma4 source address register m_ddr4 equ $ffffde ; dma4 destination address register m_dco4 equ $ffffdd ; dma4 counter m_dcr4 equ $ffffdc ; dma4 control register ; register addresses of dma5 m_dsr5 equ $ffffdb ; dma5 source address register m_ddr5 equ $ffffda ; dma5 destination address register m_dco5 equ $ffffd9 ; dma5 counter m_dcr5 equ $ffffd8 ; dma5 control register ; dma control register m_dss equ $3 ; dma source space mask (dss0-dss1) m_dss0 equ 0 ; dma source memory space 0 m_dss1 equ 1 ; dma source memory space 1 m_dds equ $c ; dma destination space mask (dds-dds1) m_dds0 equ 2 ; dma destination memory space 0 m_dds1 equ 3 ; dma destination memory space 1 m_dam equ $3f0 ; dma address mode mask (dam5-dam0) m_dam0 equ 4 ; dma address mode 0 m_dam1 equ 5 ; dma address mode 1 m_dam2 equ 6 ; dma address mode 2 m_dam3 equ 7 ; dma address mode 3 m_dam4 equ 8 ; dma address mode 4 m_dam5 equ 9 ; dma address mode 5 m_d3d equ 10 ; dma three dimensional mode m_drs equ $f800; dma request source mask (drs0-drs4) m_dcon equ 16 ; dma continuous mode m_dpr equ $60000; dma channel priority m_dpr0 equ 17 ; dma channel priority level (low) m_dpr1 equ 18 ; dma channel priority level (high) m_dtm equ $380000; dma transfer mode mask (dtm2-dtm0) m_dtm0 equ 19 ; dma transfer mode 0 m_dtm1 equ 20 ; dma transfer mode 1 m_dtm2 equ 21 ; dma transfer mode 2 m_die equ 22 ; dma interrupt enable bit m_de equ 23 ; dma channel enable bit ; dma status register m_dtd equ $3f ; channel transfer done status mask (dtd0-dtd5) m_dtd0 equ 0 ; dma channel transfer done status 0 m_dtd1 equ 1 ; dma channel transfer done status 1 m_dtd2 equ 2 ; dma channel transfer done status 2 m_dtd3 equ 3 ; dma channel transfer done status 3 m_dtd4 equ 4 ; dma channel transfer done status 4 m_dtd5 equ 5 ; dma channel transfer done status 5 m_dact equ 8 ; dma active state m_dch equ $e00; dma active channel mask (dch0-dch2) m_dch0 equ 9 ; dma active channel 0 m_dch1 equ 10 ; dma active channel 1 m_dch2 equ 11 ; dma active channel 2 ;------------------------------------------------------------------------ ; ; equates for phase locked loop (pll) ; ;------------------------------------------------------------------------ ; register addresses of pll m_pctl equ $fffffd ; pll control register ; pll control register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-10 power consumption benchmark m_mf equ $fff : multiplication factor bits mask (mf0-mf11) m_df equ $7000 ; division factor bits mask (df0-df2) m_xtlr equ 15 ; xtal range select bit m_xtld equ 16 ; xtal disable bit m_pstp equ 17 ; stop processing state bit m_pen equ 18 ; pll enable bit m_pcod equ 19 ; pll clock output disable bit m_pd equ $f00000; predivider factor bits mask (pd0-pd3) ;------------------------------------------------------------------------ ; ; equates for biu ; ;------------------------------------------------------------------------ ; register addresses of biu m_bcr equ $fffffb; bus control register m_dcr equ $fffffa; dram control register m_aar0 equ $fffff9; address attribute register 0 m_aar1 equ $fffff8; address attribute register 1 m_aar2 equ $fffff7; address attribute register 2 m_aar3 equ $fffff6; address attribute register 3 m_idr equ $fffff5 ; id register ; bus control register m_ba0w equ $1f ; area 0 wait control mask (ba0w0-ba0w4) m_ba1w equ $3e0; area 1 wait control mask (ba1w0-ba14) m_ba2w equ $1c00; area 2 wait control mask (ba2w0-ba2w2) m_ba3w equ $e000; area 3 wait control mask (ba3w0-ba3w3) m_bdfw equ $1f0000 ; default area wait control mask (bdfw0-bdfw4) m_bbs equ 21 ; bus state m_blh equ 22 ; bus lock hold m_brh equ 23 ; bus request hold ; dram control register m_bcw equ $3 ; in page wait states bits mask (bcw0-bcw1) m_brw equ $c ; out of page wait states bits mask (brw0-brw1) m_bps equ $300 ; dram page size bits mask (bps0-bps1) m_bple equ 11 ; page logic enable m_bme equ 12 ; mastership enable m_bre equ 13 ; refresh enable m_bstr equ 14 ; software triggered refresh m_brf equ $7f8000; refresh rate bits mask (brf0-brf7) m_brp equ 23 ; refresh prescaler ; address attribute registers m_bat equ $3 ; ext. access type and pin def. bits mask (bat0-bat1) m_baap equ 2 ; address attribute pin polarity m_bpen equ 3 ; program space enable m_bxen equ 4 ; x data space enable m_byen equ 5 ; y data space enable m_bam equ 6 ; address muxing m_bpac equ 7 ; packing enable m_bnc equ $f00 ; number of address bits to compare mask (bnc0-bnc3) m_bac equ $fff000; address to compare bits mask (bac0-bac11) ; control and status bits in sr m_cp equ $c00000; mask for core-dma priority bits in sr m_ca equ 0 ; carry m_v equ 1 ; overflow m_z equ 2 ; zero m_n equ 3 ; negative m_u equ 4 ; unnormalized m_e equ 5 ; extension m_l equ 6 ; limit m_s equ 7 ; scaling bit m_i0 equ 8 ; interupt mask bit 0 m_i1 equ 9 ; interupt mask bit 1 m_s0 equ 10 ; scaling mode bit 0 m_s1 equ 11 ; scaling mode bit 1 m_sc equ 13 ; sixteen_bit compatibility m_dm equ 14 ; double precision multiply f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-11 power consumption benchmark m_lf equ 15 ; do-loop flag m_fv equ 16 ; do-forever flag m_sa equ 17 ; sixteen-bit arithmetic m_ce equ 19 ; instruction cache enable m_sm equ 20 ; arithmetic saturation m_rm equ 21 ; rounding mode m_cp0 equ 22 ; bit 0 of priority bits in sr m_cp1 equ 23 ; bit 1 of priority bits in sr ; control and status bits in omr m_cdp equ $300 ; mask for core-dma priority bits in omr m_ma equ0 ; operating mode a m_mb equ1 ; operating mode b m_mc equ2 ; operating mode c m_md equ3 ; operating mode d m_ebd equ 4 ; external bus disable bit in omr m_sd equ 6 ; stop delay m_ms equ 7 ; memory switch bit in omr m_cdp0 equ 8 ; bit 0 of priority bits in omr m_cdp1 equ 9 ; bit 1 of priority bits in omr m_ben equ 10 ; burst enable m_tas equ 11 ; ta synchronize select m_brt equ 12 ; bus release timing m_ate equ 15 ; address tracing enable bit in omr. m_xys equ 16 ; stack extension space select bit in omr. m_eun equ 17 ; extensed stack underflow flag in omr. m_eov equ 18 ; extended stack overflow flag in omr. m_wrp equ 19 ; extended wrap flag in omr. m_sen equ 20 ; stack extension enable bit in omr. ;************************************************************************* ; ; equates for DSP56303 interrupts ; ; last update: june 11 1995 ; ;************************************************************************* page 132,55,0,0,0 opt mex intequ ident 1,0 if @def(i_vec) ;leave user definition as is. else i_vec equ $0 endif ;------------------------------------------------------------------------ ; non-maskable interrupts ;------------------------------------------------------------------------ i_reset equ i_vec+$00 ; hardware reset i_stack equ i_vec+$02 ; stack error i_ill equ i_vec+$04 ; illegal instruction i_dbg equ i_vec+$06 ; debug request i_trap equ i_vec+$08 ; trap i_nmi equ i_vec+$0a ; non maskable interrupt ;------------------------------------------------------------------------ ; interrupt request pins ;------------------------------------------------------------------------ i_irqa equ i_vec+$10 ; irqa i_irqb equ i_vec+$12 ; irqb i_irqc equ i_vec+$14 ; irqc i_irqd equ i_vec+$16 ; irqd ;------------------------------------------------------------------------ ; dma interrupts ;------------------------------------------------------------------------ i_dma0 equ i_vec+$18 ; dma channel 0 i_dma1 equ i_vec+$1a ; dma channel 1 i_dma2 equ i_vec+$1c ; dma channel 2 i_dma3 equ i_vec+$1e ; dma channel 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
a-12 power consumption benchmark i_dma4 equ i_vec+$20 ; dma channel 4 i_dma5 equ i_vec+$22 ; dma channel 5 ;------------------------------------------------------------------------ ; timer interrupts ;------------------------------------------------------------------------ i_tim0c equ i_vec+$24 ; timer 0 compare i_tim0of equ i_vec+$26 ; timer 0 overflow i_tim1c equ i_vec+$28 ; timer 1 compare i_tim1of equ i_vec+$2a ; timer 1 overflow i_tim2c equ i_vec+$2c ; timer 2 compare i_tim2of equ i_vec+$2e ; timer 2 overflow ;------------------------------------------------------------------------ ; essi interrupts ;------------------------------------------------------------------------ i_si0rd equ i_vec+$30 ; essi0 receive data i_si0rde equ i_vec+$32 ; essi0 receive data w/ exception status i_si0rls equ i_vec+$34 ; essi0 receive last slot i_si0td equ i_vec+$36 ; essi0 transmit data i_si0tde equ i_vec+$38 ; essi0 transmit data w/ exception status i_si0tls equ i_vec+$3a ; essi0 transmit last slot i_si1rd equ i_vec+$40 ; essi1 receive data i_si1rde equ i_vec+$42 ; essi1 receive data w/ exception status i_si1rls equ i_vec+$44 ; essi1 receive last slot i_si1td equ i_vec+$46 ; essi1 transmit data i_si1tde equ i_vec+$48 ; essi1 transmit data w/ exception status i_si1tls equ i_vec+$4a ; essi1 transmit last slot ;------------------------------------------------------------------------ ; sci interrupts ;------------------------------------------------------------------------ i_scird equ i_vec+$50 ; sci receive data i_scirde equ i_vec+$52 ; sci receive data with exception status i_scitd equ i_vec+$54 ; sci transmit data i_sciil equ i_vec+$56 ; sci idle line i_scitm equ i_vec+$58 ; sci timer ;------------------------------------------------------------------------ ; host interrupts ;------------------------------------------------------------------------ i_hrdf equ i_vec+$60 ; host receive data full i_htde equ i_vec+$62 ; host transmit data empty i_hc equ i_vec+$64 ; default host command ;----------------------------------------------------------------------- ; interrupt ending address ;------------------------------------------------------------------------ i_intend equ i_vec+$ff ; last address of interrupt vector space f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index index-1 a ac electrical characteristics 2-4 address bus 1-1 address trace mode 2-25 , 2-27 applications iv arbitration bus timings 2-27 b benchmark test algorithm a-1 block diagram i bootstrap rom iii boundary scan (jtag port) timing diagram 2-46 bus acquisition timings 2-28 address 1-2 control 1-1 data 1-2 external address 1-5 external data 1-5 multiplexed 1-2 non-multiplexed 1-2 release timings 2-28 , 2-29 c clock 1-1 , 1-4 external 2-4 clocks internal 2-4 crystal oscillator circuits 2-5 d data bus 1-1 data memory expansion iv data strobe (ds) 1-2 dc electrical characteristics 2-3 de signal 1-18 debug event signal ( de signal) 1-18 debug mode entering 1-18 external indication 1-18 debug support iii design considerations electrical 4-2 , 4-3 pll 4-5 power consumption 4-4 thermal 4-1 documentation list iv double data strobe 1-2 dram controller iv out of page read access 2-23 wait states selection guide 2-20 write access 2-24 page mode read accesses 2-19 wait states selection guide 2-16 write accesses 2-19 refresh access 2-24 dsp56300 family manual iv DSP56303 block diagram i technical data iv user?s manual iv e electrical design considerations 4-2 , 4-3 enhanced synchronous serial interface (essi) iii , 1-1 , 1-2 , 1-13 , 1-14 receiver timing 2-42 transmitter timing 2-41 external address bus 1-5 external bus control 1-5 , 1-6 , 1-7 external bus synchronous timings (sram access) 2-25 external clock operation 2-4 external data bus 1-5 external interrupt timing (negative edge-triggered) 2-11 external level-sensitive fast interrupt timing 2-10 external memory access (dma source) timing 2-12 external memory expansion port 2-13 external memory expansion port 1-5 f functional groups 1-2 functional signal groups 1-1 g general-purpose input/output (gpio) iii , 1-2 ground 1-1 , 1-3 pll 1-3 h host interface (hi08) iii , 1-1 , 1-2 , 1-9 , 1-10 , 1-11 , 1-12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index index-2 host port control register (hpcr) 1-10 , 1-12 host port configuration 1-9 usage considerations 1-9 host port control register (hpcr) 1-10 , 1-12 host request double 1-2 single 1-2 host request (hr) 1-2 i information sources iv instruction cache iii internal clocks 2-4 interrupt and mode control 1-1 , 1-8 interrupt control 1-8 interrupt timing 2-7 external level-sensitive fast 2-10 external negative edge-triggered 2-11 synchronous from wait state 2-11 j joint test action group (jtag) interface 1-18 jtag iii jtag port reset timing diagram 2-46 timing 2-46 jtag/once interface signals debug event signal ( de signal) 1-18 jtag/once port 1-1 , 1-2 m map-bga 3-1 ball list by name 3-15 ball list by number 3-12 mechanical drawing 3-19 molded array process-ball grid drawing (bottom) 3-11 molded array process-ball grid drawing (top) 3-10 maximum ratings 2-1 , 2-2 memory expansion port iii mode control 1-8 mode select timing 2-7 multiplexed bus 1-2 multiplexed bus timings read 2-35 write 2-36 n non-multiplexed bus 1-2 non-multiplexed bus timings read 2-33 write 2-34 o off-chip memory iii once module iii debug request 2-47 on-chip dram controller iv on-chip emulation (once) module interface 1-18 on-chip emulation module iii on-chip memory iii operating mode select timing 2-11 p package 144-pin tqfp 3-1 196-pin map-bga 3-1 map-bga description 3-10 , 3-11 , 3-12 , 3-15 , 3-19 tqfp description 3-2 , 3-3 , 3-4 , 3-6 , 3-9 phase-lock loop (pll) 1-1 , 2-6 design considerations 4-5 performance issues 4-5 pll 1-4 port a 1-1 , 1-5 , 2-13 port b 1-1 , 1-2 , 1-11 port c 1-1 , 1-2 , 1-13 port d 1-1 , 1-2 , 1-14 port e 1-1 power 1-1 , 1-2 , 1-3 power consumption design considerations 4-4 power consumption benchmark test a-1 power management iv program memory expansion iv program ram iii r recovery from stop state using irqa 2-12 reset clock signals 1-4 interrupt signals 1-8 jtag signals 1-18 mode control 1-8 once signals 1-18 pll signals 1-4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index index-3 reset timing 2-7 , 2-9 synchronous 2-10 rom, bootstrap iii s serial communication interface (sci) iii , 1-1 , 1-2 , 1-16 asynchronous mode timing 2-38 synchronous mode timing 2-38 signal groupings 1-1 signals 1-1 functional grouping 1-2 single data strobe 1-2 sram read access 2-15 support iv write access 2-15 stop mode iv stop state recovery from 2-12 stop timing 2-7 supply voltage 2-2 switch mode iii synchronous bus timings sram 2 wait states 2-26 sram 1 wait state (bcr controlled) 2-26 synchronous interrupt from wait state timing 2-11 synchronous reset timing 2-10 t target applications iv test access port (tap) iii timing diagram 2-46 test clock ( tclk ) input timing diagram 2-45 thermal design considerations 4-1 timer event input restrictions 2-43 timers 1-1 , 1-2 , 1-17 interrupt generation 2-43 tqfp 3-1 mechanical drawing 3-9 pin list by name 3-6 pin list by number 3-4 pin-out drawing (bottom) 3-3 pin-out drawing (top) 3-2 w wait mode iv world wide web iv x x-data ram iii y y-data ram iii f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
DSP56303/d, rev. 10 how to reach us: usa / europe / locations not listed: motorola literature distribution p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street tai po industrial estate, tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors/ information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. once and digital dna are trademarks of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 1996, 2004 ordering information consult a motorola semiconductor sales office or authorized distributor to determine product availability and place an order. part supply voltage package type pin count core frequency (mhz) order number DSP56303 3.3 v i/o thin quad flat pack (tqfp) 144 100 DSP56303pv100 molded array process-ball grid array (map-bga) 196 100 DSP56303vf100 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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